Combining Design Space Exploration with Task Scheduling of Moldable Streaming Tasks on Reconfigurable Platforms

Keller, Jörg; Litzinger, Sebastian; Keßler, Christoph

doi:10.1007/978-3-030-79025-7_7

Cited by 2 publications

(7 citation statements)

References 15 publications

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“…Yet, the design goal there is often not to place the maximum number of cores, but a fixed combination of different cores that is optimal with respect to a required throughput or power consumption. This is also true for [9] where a placement heuristic for two different core types is given, which we generalize to K > 2 core types in this paper. While [9], by design 1 , places similar cores as closely as possible, it does not formalize proximity, only considers two core types, and does not use that placement, but the achieved core counts serve as a lower bound in a design space exploration.…”

Section: Related Workmentioning

confidence: 88%

“…This is also true for [9] where a placement heuristic for two different core types is given, which we generalize to K > 2 core types in this paper. While [9], by design 1 , places similar cores as closely as possible, it does not formalize proximity, only considers two core types, and does not use that placement, but the achieved core counts serve as a lower bound in a design space exploration.…”

Section: Related Workmentioning

confidence: 88%

“…A (system) configuration (p 1 , ..., p K ) ∈ N K 0 describes a heterogeneous multicore system with K core types that is 1 The placement heuristic in [9] is actually a variant of the special case of the corner heuristic (Sect. III) for K = 2, where in [9] the placement of the two different core types instead starts from opposite corners of the chip rectangle, but otherwise proceeds in the same way. 2 Rotations further increase the solution space, unless all rectangles are squares.…”

Section: Corner and Onion Packing Heuristics A Problem Formulationmentioning

confidence: 99%

“…Dominated configurations are uninteresting, because they are not Paretooptimal with respect to the number of cores that can be accommodated. Hence, we will only keep the non-dominated configurations, and it will be up to the optimized software [9] to decide if the additional core(s) are used or powered down.…”

Section: Corner and Onion Packing Heuristics A Problem Formulationmentioning

confidence: 99%

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Packing Multiple Types of Cores for Energy-Optimized Heterogeneous Hardware-Software Co-Design of Moldable Streaming Computations

2023

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For fixed-application scenarios in embedded soft-realtime computing, the ideal (w.r.t. energy consumption) heterogeneous multi-core CPU design within given chip dimensions can be configured by composing it from given pre-layouted, rectangular chip submodules for each of a number K > 1 of core types, where K in practice is a small constant. For example, K = 2 in traditional ARM big.LITTLE designs. Nevertheless, even better solutions might be achieved for K>2, and many feasible combinations can exist. For this purpose, we investigate finding all combinations of instances of K > 1 different types of given axis-parallel rectangles that can be packed within a given fixed-size 2D rectangle, and we propose two new packing heuristics: the corner heuristic for K ≤ 4, and the onion heuristic for larger K. Both heuristics strive to pack cores of the same type close together, to simplify implementation of on-chip bus and shared cache structures. The core combinations can be used in co-optimizing chip configuration, task mapping and scheduling for stream processing applications. We evaluate the corner heuristic for a number of different types of ARM softcores and chip dimensions, and show that it outperforms strip packing techniques from the literature and yields similar results to an advanced rectpack heuristic allowing rotation, though these do not try to pack similar cores closely. INDEX TERMSPacking rectangles, heterogeneous multi-core CPU, design space exploration, hardwaresoftware co-design VOLUME 4, 2016

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Section: Related Workmentioning

confidence: 88%

Section: Related Workmentioning

confidence: 88%

Section: Corner and Onion Packing Heuristics A Problem Formulationmentioning

confidence: 99%

Section: Corner and Onion Packing Heuristics A Problem Formulationmentioning

confidence: 99%

See 2 more Smart Citations

Packing Multiple Types of Cores for Energy-Optimized Heterogeneous Hardware-Software Co-Design of Moldable Streaming Computations

2023

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“…This article is an extended version of[1]. In particular, we add experiments with more than 2 core types, contrast upper bound on usable cores with a lower bound, generalize the crown scheduler to non-power of 2 group sizes, and analyze possible threats to validity.…”

mentioning

confidence: 99%

Integrating Energy-Optimizing Scheduling of Moldable Streaming Tasks with Design Space Exploration for Multiple Core Types on Configurable Platforms

Keller

Litzinger

Keßler

2022

J Sign Process Syst

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Design space exploration of a configurable, heterogeneous system for a given application with required throughput searches for a combination of cores or softcores with different architectures that can be accommodated within the given ASIC or FPGA area and that achieves the required throughput and optimizes power consumption. For a soft real-time streaming application, modeled as a task graph with internally parallelizable streaming tasks, this requires assigning a core type and quantity and DVFS frequency level to each task, which implies task runtime and energy consumption, and mapping and scheduling the tasks, such that the throughput requirement is met. We tightly integrate such static scheduling for stream processing applications with design space exploration of the best heterogeneous core combination, and solve the resulting combined optimization problem by an integer linear program (ILP). We evaluate our solution for different numbers of core types on synthetic and application-based task graphs, and demonstrate improvements of up to 34.8% for ARM big and LITTLE cores, and 70.5% for 3 different core types.

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Combining Design Space Exploration with Task Scheduling of Moldable Streaming Tasks on Reconfigurable Platforms

Cited by 2 publications

References 15 publications

Packing Multiple Types of Cores for Energy-Optimized Heterogeneous Hardware-Software Co-Design of Moldable Streaming Computations

Packing Multiple Types of Cores for Energy-Optimized Heterogeneous Hardware-Software Co-Design of Moldable Streaming Computations

Integrating Energy-Optimizing Scheduling of Moldable Streaming Tasks with Design Space Exploration for Multiple Core Types on Configurable Platforms

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