Common-mode Voltage Reduction of Three Level Four Leg PWM Converter

Abstract

This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

Experimental evaluation of model predictive current control for a modified three‐level four‐leg indirect matrix converter

“…On top of that, multi‐objective control such as minimisation of reactive power is only possible by adding an additional cascade of PI controller which may increase the complexity of the tuning and the computational burden. In [15–17], a PWM scheme has been proposed. Unlike conventional PWM, the control of zero‐sequence current is quite complex.…”