Common-Mode Voltage Reduction Pulsewidth Modulation Techniques for Three-Phase Grid-Connected Converters

Hou, Chung-Chuan; Shih, Chih-Chung; Cheng, Po-Tai; Hava, Ahmet M.

doi:10.1109/tpel.2012.2196712

Cited by 236 publications

(111 citation statements)

References 9 publications

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“…A basic principle of the CMV reduction in normal 6-switch PWM rectifiers is to eliminate the zero vectors 000 and 111 in the modulation so that the values of ±v o /2 can be avoided. Thus, the RMS value of the common mode voltage in a 6-switch rectifier is also reduced by avoiding the zero vectors 000 and 111 [24]- [26]. Meanwhile, in post-fault PWM rectifiers, the CMV reduction methods should be reconsidered due to the different topologies.…”

Section: Performance Of the Common Mode Voltagementioning

confidence: 99%

“…When a high-frequency common mode voltage (CMV) is present across the parasitic capacitance, excessive leakage currents are produced. These leakage currents result in many issues related to safety of people in contact with PV modules, and degrades the system reliability [24]- [26]. Therefore, common mode voltage should be suppressed to improve the reliability of post-fault rectifiers and personnel safety.…”

Section: Introductionmentioning

confidence: 99%

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Performance Analysis and Comparison of Post-Fault PWM Rectifiers Using Various Space Vector Modulation Methods

Zhu¹,

Zeng²,

Zhao³

2016

Journal of Power Electronics

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In this paper, some crucial performance characteristics related to the operational reliability of the post-fault Pulse Width Modulated (PWM) rectifiers, such as line current harmonic distortion, Common Mode Voltage (CMV), and current stress on the capacitors, are fully investigated. The aforementioned performance characteristics of post-fault rectifiers are highly dependent on the utilized space vector modulation (SVM) schemes, which are also examined. Detailed analyses of the three most commonly used SVM schemes for post-fault PWM rectifiers are provided, revealing the major differences in terms of the zero vector synthesis approaches. To compare the performances of the three SVM schemes, the operating principles of a post-fault rectifier are presented with various SVM schemes. Using analytical and numerical methods in the time domain, the performances of the line current distortion, common mode voltage and capacitor current are evaluated and compared for each SVM scheme. The proposed analysis demonstrates that the zero vector synthesis approaches of the considered methods have significant impacts on the performance characteristics of rectifiers. In addition, the advantages and disadvantages of the proposed SVM schemes are discussed. The experimental results verify the effectiveness and validity of the proposed analysis.

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Section: Performance Of the Common Mode Voltagementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Performance Analysis and Comparison of Post-Fault PWM Rectifiers Using Various Space Vector Modulation Methods

Zhu¹,

Zeng²,

Zhao³

2016

Journal of Power Electronics

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“…However, methods using software that only changes the switching patterns, are considerably simpler to implement, and do not result in additional size and costs. Hence, research has now been focused on the development of various PWM algorithms for the reduction of CMV, known as reduced CMV-PWM (RCMV-PWM) algorithms [7]- [16]. RCMV-PWM algorithms can be divided into three groups: active zero state PWM (AZSPWM) algorithms [7]- [16], remote state PWM (RSPWM) algorithms [14], and near state PWM (NSPWM) algorithms [12], [14], [16].…”

Section: Introductionmentioning

confidence: 99%

“…Hence, research has now been focused on the development of various PWM algorithms for the reduction of CMV, known as reduced CMV-PWM (RCMV-PWM) algorithms [7]- [16]. RCMV-PWM algorithms can be divided into three groups: active zero state PWM (AZSPWM) algorithms [7]- [16], remote state PWM (RSPWM) algorithms [14], and near state PWM (NSPWM) algorithms [12], [14], [16]. In addition, the AZSPWM algorithms can be further divided into AZSPWM1 [7]- [14], [16], AZSPWM2 [13]- [15], and AZSPWM3 [8], [13], [14] algorithms.…”

Section: Introductionmentioning

confidence: 99%

A New Active Zero State PWM Algorithm for Reducing the Number of Switchings

Yun¹,

Baik²,

Kim³

et al. 2017

Journal of Power Electronics

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To reduce common-mode voltage (CMV), various reduced CMV pulse width modulation (RCMV-PWM) algorithms have been proposed, including active zero state PWM (AZSPWM) algorithms, remote state PWM (RSPWM) algorithms, and near state PWM (NSPWM) algorithms. Among these algorithms, AZSPWM algorithms can reduce CMV, but they increase the number of switchings compared to the conventional space vector PWM (CSVPWM). This paper presents a new AZSPWM algorithm for reductions in both the CMV and total number of switchings in BLAC motor drives. Since the proposed AZSPWM algorithm uses only active voltage vectors for motor control, it reduces CMV by 1/3 compared to CSVPWM. The proposed AZSPWM algorithm also reduces the total number of switchings compared to existing AZSPWM algorithms by eliminating the switchings required from one sector to the next. The performance of the proposed algorithm is verified by analyses, simulations, and experimental results.

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“…3레벨 4레그 PWM 컨버터의 커먼 모드 전압 저감 [3] . 이와 같은 CMC를 줄이기 위해 통상 사용하 는 방법에는 두 가지가 있는데, 하나는 커먼 모드 필 터 등의 수동 소자를 이용하는 것이고 [4] , 다른 하나는 PWM 스위칭 패턴을 바꾸는 방법이다 [5][6][7][8][9][10] . 4레그 PWM 컨버터의 CMV는 식 (1)과 같이 표시된 다 [10] .…”

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Common-mode Voltage Reduction of Three Level Four Leg PWM Converter

Chee

Kim

et al. 2014

The Transactions of the Korean Institute of Power Electronics

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This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

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Common-Mode Voltage Reduction Pulsewidth Modulation Techniques for Three-Phase Grid-Connected Converters

Cited by 236 publications

References 9 publications

Performance Analysis and Comparison of Post-Fault PWM Rectifiers Using Various Space Vector Modulation Methods

Performance Analysis and Comparison of Post-Fault PWM Rectifiers Using Various Space Vector Modulation Methods

A New Active Zero State PWM Algorithm for Reducing the Number of Switchings

Common-mode Voltage Reduction of Three Level Four Leg PWM Converter

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