Communication architecture design for reconfigurable multimedia SoC platform

Abstract

Memory and communication architecture have a significant impact on the performance, cost, and power of complex multiprocessor system-on-chip designs. In this paper, we present an automated bus matrix synthesis flow for efficient transaction-level design space exploration of communication architecture in a reconfigurable multimedia system-on-chip platform. Specifically, we consider hardware interface selection problem, which has significant effect on the overall cost of area and power. We propose a method to solve such hardware interface selection problem through static analysis of communication behavior. We experiment with JPEG encoder and H.264 encoder examples and the results show the reduction of area by 56.91% and power by 48.61% of bus matrix with 0.58% performance overhead on average compared to the case of maximum performance. According to our HW interface selection algorithm, we also experiment MPEG4 video decoder example. And the result is evaluated on the FPGA prototyping board.

Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications

“…An automatic bus matrix synthesis flow of a reconfigurable architecture is proposed in [18]. The external DRAM is implemented as off-chip memory to store encoded (or reconstructed) images, and the others are allocated in the internal SRAM.…”