Compact 0.7-V CMOS voltage/current reference with 54/29-ppm/&amp;#x00B0;C temperature coefficient

Park, Yoon-Suk; Kim, Hyoung-Rae; Oh, Jae-Hyuk; Choi, Yoon-Kyung; Kong, Bai-Sun

doi:10.1109/socdc.2009.5423852

Cited by 16 publications

(4 citation statements)

References 6 publications

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“…1(c) right), can also lead to a CWT current. The subtraction can be done (i) between a PTAT current and its purely temperature-dependent component [32] or (ii) between two different currents [33]- [35]. Besides, the weighted sum is performed with a PTAT current, implemented with bipolar transistors as the ratio of a difference of base-to-emitter voltages ∆V BE and a resistance, and a CTAT current obtained by the ratio of a ∆V GS [36] or a V BE [37], [38] and a resistance.…”

Section: B Cwt Current Reference Topologiesmentioning

confidence: 99%

A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-$μ$m with 0.1-nA PTAT and 1.1-$μ$A CWT 38-ppm/$^\circ$C Designs

Lefebvre,

Bol

2022

Preprint

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The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of these requirements with a handful of transistors, current references remain rather complex, requiring significant design time and silicon area. In this paper, we present a family of simple current references consisting of a two-transistor (2T) ultra-low-power voltage reference, buffered onto a voltage-to-current converter by a single transistor. Two topologies are fabricated in a 0.18-µm partially-depleted silicon-on-insulator (SOI) technology and measured over 10 dies. First, a 7T nA-range proportional-to-absolutetemperature (PTAT) reference intended for constant-gm biasing of subthreshold operational amplifiers demonstrates a 0.096-nA current with a line sensitivity (LS) of 1.48 %/V, a temperature coefficient (TC) of 0.75 %/ • C, and a variability (σ/µ) of 1.66 %. Then, two 4T+1R µA-range constant-with-temperature (CWT) references with (resp. without) TC calibration exhibit a 1.09-µA (resp. 0.99-µA) current with a 0.21-%/V (resp. 0.20-%/V) LS, a 38-ppm/ • C (resp. 290-ppm/ • C) TC, and a 0.87-% (resp. 0.65-%) (σ/µ). In addition, portability to common scaled CMOS technologies, such as 65-nm bulk and 28-nm fully-depleted SOI, is discussed and validated through post-layout simulations.

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Section: B Cwt Current Reference Topologiesmentioning

confidence: 99%

A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-$μ$m with 0.1-nA PTAT and 1.1-$μ$A CWT 38-ppm/$^\circ$C Designs

Lefebvre,

Bol

2022

Preprint

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“…It is very common to use a process, voltage and temperature (PVT) insensitive circuitry for generating stable reference current [13,14,15]. In this work, we introduce a basic reference-current-generator with temperature compensation into the PDE design.…”

Section: Proposed Pde Circuit Employing Referencecurrent-generator (Tmentioning

confidence: 99%

“…Without static power consumption, the delay change due to process variations (3% on the transistor's size for instance) is less than one third compared to that of conventional PDE circuits. Another type of PDE circuit is proposed employing a reference-current-generator [13,14,15], in which the reference current is digitally programmed by a Neuron-MOS-like transistor. With the consideration of temperature fluctuation from 25 o C to 75 o C, the delay change is less than 0.1%.…”

Section: Introductionmentioning

confidence: 99%

A feasibility study on robust programmable delay element design based on neuron-MOS mechanism

Zhang

Kaneko

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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The feasibility of programmable delay elements (PDEs) design based on Neuron-MOS mechanism is investigated in this work. By applying the capacitor coupling technology, the charging/discharging current of a clock buffer can be digitally programmed to generate various switching delay without static power consumption. No any additional transistor is introduced into the charging/discharging path, that reduces the performance fluctuation due to process variations for MOS transistors. From the circuit simulation results, the delay change of proposed PDE is less than one third compared to that of the conventional PDE circuits. In order to reduce the temperature sensitivity, another Neuron-MOSbased PDE circuit is also suggested by employing a temperature insensitive reference-current-generator. This type of PDE circuit achieves a delay change within 0.1% when the temperature fluctuates from 25 o C to 75 o C. In general, both types of suggested PDE circuits achieve better or fair performances over the robustness, power consumption and delay range.

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“…3) PTAT+CTAT: they exploit the weighted sum between PTAT and CTAT current generators. The principle of the PTAT generation relies on ∆V BE /R (using BJTs); on the other hand, the CTAT temperature dependency is obtained by using the ratio between ∆V GS (or a V BE of a BJT) of NMOS transistors and a resistor [12], [14], [15], [19], [24], [27], [31], [32].…”

mentioning

confidence: 99%

A 6.3-ppm/°C, 100-nA Current Reference With Active Trimming in 28-nm Bulk CMOS Technology

2022

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This paper introduces a current reference based on ∆V GS generation principle and adopts integrated poly-p+ resistors and a nW-power OTA to reduce the line sensitivity. Implemented in a 28-nm standard CMOS technology, the circuit provides a nominal current equal to 100nA and operates down to 0.6 V with a line sensitivity equal to 1.2 %/V in the range [0.8-1.8] V and a temperature coefficient equal to 6.3 ppm/°C in the range [10-90]°C. Comparison with the state-of-the-art confirms the validity of the proposed solution and its suitability to be exploited in ultra-low-power and area-constrained applications.INDEX TERMS Current reference, low voltage, low power, area-efficient, Internet of Things, sensor nodes, implanted biomedical devices NOMENCLATURE

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Compact 0.7-V CMOS voltage/current reference with 54/29-ppm/°C temperature coefficient

Cited by 16 publications

References 6 publications

A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-$μ$m with 0.1-nA PTAT and 1.1-$μ$A CWT 38-ppm/$^\circ$C Designs

A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-$μ$m with 0.1-nA PTAT and 1.1-$μ$A CWT 38-ppm/$^\circ$C Designs

A feasibility study on robust programmable delay element design based on neuron-MOS mechanism

A 6.3-ppm/°C, 100-nA Current Reference With Active Trimming in 28-nm Bulk CMOS Technology

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