Compact and Power Conscious Private-key Cryptosystem for Wireless Devices

Rejeb, Jalel; Kaginele, Smitha; Lee, Thuy

doi:10.1109/icwmc.2006.33

Cited by 3 publications

(2 citation statements)

References 12 publications

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“…AES can be implemented by using various design architectural models that could be used to optimize the power, area and speed. As noted in Farhan et al (2004), Hamalainen et al (2005), Good and Benaissa (2005), Rejeb et al (2006), memory-based architecture designs take less design time and less complex design strategy. However, it occupies more area, consumes more power and requires more access time.…”

Section: Literature Surveymentioning

confidence: 99%

“…Different memory-based designs were discussed in Lookup Table (LUT) method by Farhan et al (2004), Hamalainen et al (2005), Good and Benaissa (2005), Verbauwhede et al (2003), Hodjat and Verbauwhede (2004) and embedded design by Rejeb et al (2006). Further, basic digital circuits like encoder, decoder structures were discussed by Fischer and Drutarovský (2001), and reconfigurable design by Bertoni et al (2004), Zhang et al (2007) to reduce the complexity of the design.…”

Section: Literature Surveymentioning

confidence: 99%

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Design and implementation of power and area optimized AES architecture on FPGA for IoT application

Rajasekar

Mangalam

2020

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Purpose The growing trends in the usage of hand held devices necessitate the need to design them with low power consumption and less area design. Besides, information security is gaining enormous importance in information transmission and data storage technology. In addition, today’s technology world is connected, communicated and controlled via the Internet of Things (IoT). In many applications, the most standard and widely used cryptography algorithm for providing security is Advanced Encryption Standard (AES). This paper aims to design an efficient model of AES cryptography for low power and less area. Design/methodology/approach First, the main issues related to less area and low power consumption in the AES encryption core are addressed. To implement optimized AES core, the authors proposed optimized multiplicative inverse, affine transforms and Xtime multipliers functions, which are the core function of AES’s core. In addition, to achieve the high throughput, it uses the multistage pipeline and resource reuse architectures for SBox and Mixcolumn of AES. Findings The results of optimized AES architecture have revealed that the multistage pipe line and resource sharing are optimal design model in Field Programmable Gate Array (FPGA) implementation. It could provide high security with low power and area for IoT and wireless sensors networks. Originality/value This proposed optimized modified architecture has been implemented in FPGA to calculate the power, area and delay parameters. This multistage pipeline and resource sharing have promised to minimize the area and power.

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Section: Literature Surveymentioning

confidence: 99%

Section: Literature Surveymentioning

confidence: 99%

Design and implementation of power and area optimized AES architecture on FPGA for IoT application

Rajasekar

Mangalam

2020

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Design of new tiny circuits for AES encryption algorithm

Dalmisli

Örs

2009

2009 3rd International Conference on Signals, Circuits and Systems (SCS)

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A Novel Byte-Substitution Architecture for the AES Cryptosystem

Hossain

Ali

2015

PLoS ONE

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The performance of Advanced Encryption Standard (AES) mainly depends on speed, area and power. The S-box represents an important factor that affects the performance of AES on each of these factors. A number of techniques have been presented in the literature, which have attempted to improve the performance of the S-box byte-substitution. This paper proposes a new S-box architecture, defining it as ultra low power, robustly parallel and highly efficient in terms of area. The architecture is discussed for both CMOS and FPGA platforms, and the pipelined architecture of the proposed S-box is presented for further time savings and higher throughput along with higher hardware resources utilization. A performance analysis and comparison of the proposed architecture is also conducted with those achieved by the existing techniques. The results of the comparison verify the outperformance of the proposed architecture in terms of power, delay and size.

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Compact and Power Conscious Private-key Cryptosystem for Wireless Devices

Cited by 3 publications

References 12 publications

Design and implementation of power and area optimized AES architecture on FPGA for IoT application

Design and implementation of power and area optimized AES architecture on FPGA for IoT application

Design of new tiny circuits for AES encryption algorithm

A Novel Byte-Substitution Architecture for the AES Cryptosystem

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