Compact Millimeter-Wave CMOS Wideband Three-Transmission-Zeros Bandstop Filter Using a Single Coupled-Line Unit

Design of on‐chip resonator using distributed capacitors in 0.13‐μm (Bi)‐CMOS technology

“…For proof-of-concept, the resonators are fabricated in a standard 0.13-μm (Bi)-CMOS technology. The size of the resonator without the testing pads is 0.017 mm 2 . It can generate a resonance at 47 GHz.…”

“…Resonator is perhaps one of the most fundamental building blocks for all passive devices, ranging from filter to coupler. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20] Generally speaking, the resonators can be implemented using either distributed-or lumped-element approaches. The lumped-element approach is preferred for miniaturized on-chip passive devices operating at microwave frequencies.…”

“…The lumped-element approach is preferred for miniaturized on-chip passive devices operating at microwave frequencies. [1][2][3][4][5][6][7][8][9] However, the distributed-element approach also has some distinguished features, especially the operation frequency increases to millimeter-wave (mm-wave) region. Recently, several interesting works have been published in the literature to address different design issues related to on-chip passive device implementation.…”

Compact Millimeter-Wave Bandpass Filters Using Quasi-Lumped Elements in 0.13-$\mu$ m (Bi)-CMOS Technology for 5G Wireless Systems

“…When C 1 , L 1 , and L 2 are chosen, the susceptance slope parameter b is fixed as well. Then, the values of C 2 and C 3 can be decided based on (13) and (14) with given design targets for g 0 , g 1 , FBW, and Q ex . The calculated S-parameters of the resonator and the BPF are given in Fig.…”

“…As far as on-chip filter designs are concerned, several design tradeoffs need to be considered to satisfy different design specifications, such as miniaturized physical size and reduced insertion loss. Several prior works can be found in the literature on this regard, which includes bandstop [13], lowpass [14], [15], and BPFs [16]- [28] design in standard siliconbased technologies. By miniaturizing physical dimensions of 0018-9480 © 2019 IEEE.…”