Compact modeling and simulation of accelerated circuit aging

Self-healing integrated circuits/systems in semiconductor nanometer technologies

“…Faster traps (i.e., shorter capture time constants) have a higher probability of getting filled compared to the slower traps. Furthermore, the trap occupation probability increases with gate bias and temperature [40].…”

“…According to trapping-detrapping theory, traps located in the gate dielectric or at the silicon interface capture and reemit some of the charge carriers responsible (Figure 2.7), for the current flowing between source and drain of a MOSFET [15]. When a trap captures a charged carrier, the transistor's threshold voltage increases, which constitutes the stress phase [40]. On the other hand, when the trapped carriers are released due to positive V GS , it results in recovery and leads to a decrease in the number of occupied traps as seen in Figure 2.7(b) [40].…”

“…When a trap captures a charged carrier, the transistor's threshold voltage increases, which constitutes the stress phase [40]. On the other hand, when the trapped carriers are released due to positive V GS , it results in recovery and leads to a decrease in the number of occupied traps as seen in Figure 2.7(b) [40]. Previous research has revealed that the statistical probability of trapping depends on the time constants, the number of traps, the location of traps and the trap energies.…”