Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics

Yang, Xiudi; Bardon, M. Garcia; Kaczer, B.; Alam, Nur K.; Ragnarsson, L.-Å.; Kaczmarek, Krzysztof T.; Parvais, B.; Groeseneken, G.; Houdt, J. Van

doi:10.1109/ted.2021.3049761

Cited by 24 publications

(14 citation statements)

References 32 publications

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“…We have obtained a maximum of 50 numbers of memory states and a minimum of 26 numbers of memory states for a single device. This variation in available conducting states can be attributed to charge trapping, channel percolation, and nucleation growth domain dynamics (Xiang et al, 2020;Xiang et al, 2021). Figure 4C shows the gradual change in channel conductance during potentiation and depression.…”

Section: Methodsmentioning

confidence: 98%

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Baig

Qiu

et al. 2022

Front. Nanotechnol.

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This work presents 2-bits/cell operation in deeply scaled ferroelectric finFETs (Fe-finFET) with a 1 µs write pulse of maximum ±5 V amplitude and WRITE endurance above 109 cycles. Fe-finFET devices with single and multiple fins have been fabricated on an SOI wafer using a gate first process, with gate lengths down to 70 nm and fin width 20 nm. Extrapolated retention above 10 years also ensures stable inference operation for 10 years without any need for re-training. Statistical modeling of device-to-device and cycle-to-cycle variation is performed based on measured data and applied to neural network simulations using the CIMulator software platform. Stochastic device-to-device variation is mainly compensated during online training and has virtually no impact on training accuracy. On the other hand, stochastic cycle-to-cycle threshold voltage variation up to 400 mV can be tolerated for MNIST handwritten digits recognition. A substantial inference accuracy drop with systematic retention degradation was observed in analog neural networks. However, quaternary neural networks (QNNs) and binary neural networks (BNNs) with Fe-finFETs as synaptic devices demonstrated excellent immunity toward the cumulative impact of stochastic and systematic variations.

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Section: Methodsmentioning

confidence: 98%

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Baig

Qiu

et al. 2022

Front. Nanotechnol.

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“…The large capacitance or larger V DS slightly increases the self-turn-off time, which is due to the increasing time of charge depletion. In addition to the intrinsic effect caused by the ferroelectric switching and charge redistribution, some extrinsic factors, such as the measurement circuit and device structure, as well as charge trapping, may increase the turn-on/off time of the FeFET. ,, …”

Section: Resultsmentioning

confidence: 99%

Ultralow Subthreshold Swing of a MOSFET Caused by Ferroelectric Polarization Reversal of Hf_0.5Zr_0.5O₂ Thin Films

Wang,

Liu,

Luo

et al. 2023

ACS Appl. Mater. Interfaces

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The emergence of complementary metal−oxide semiconductor (CMOS)-compatible HfO 2 -based ferroelectric materials provides a promising way to achieve ferroelectric field-effect transistors (FeFETs) with a steep subthreshold swing (SS) reduced to below the Boltzmann thermodynamics limit (∼60 mV/dec at room temperature), which has important implications for lowering power consumption. In this work, a metal−oxide-semiconductor field-effect transistor (MOSFET) is connected with Hf 0.5 Zr 0.5 O 2 (HZO)-based ferroelectric capacitors with different capacitances. By adjusting the capacitance of ferroelectric capacitors, an ultralow SS of ∼0.34 mV/dec in HfO 2 -based FeFETs can be achieved. More interestingly, by designing the sweeping voltage sequences, the SS can be adjusted to be 0 mV/dec with the drain current ranging over six orders of magnitude, and the threshold voltage for turning on the MOSFET can be further reduced. The manipulated SS could be attributed to the evolution of ferroelectric switching. Our work contributes to understanding the origin of ultralow SS in ferroelectric MOSFETs and the realization of low-power devices.

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“…. (13) This indicates that the discussion so far is still valid. However, when A FE /A IL is extremely small (e.g., less than 1/100), the effect of the right side of ( 13) has to be considered, which is equivalent to interface charges discussed in Sec.…”

Section: A Mfis-type and Mfmis-type Fefetsmentioning

confidence: 91%

“…S. L. Miller and P. J. McWhorter [8] have summarized a set of the governing equations of FeFETs, but the behavior of MW has not been sufficiently discussed. Most research works discussing about MW so far have been studied through self-consistent simulations solving a set of governing equations [10][11][12][13]; however, such a numerical approach provides limited information since the role of each material parameter as well as the underlying physical mechanism is difficult to interpret accurately. One approximate expression MW = 2EctFE(1−EcεFEε0/ηPs) (P s : spontaneous polarization; η: squareness of hysteresis loop; t FE : ferroelectric thickness; ε 0 : vacuum permittivity) has been proposed by Lue et al [14], but this expression only holds at large P s otherwise the expression will be unrealistically negative.…”

Section: Introductionmentioning

confidence: 99%

Memory Window in Ferroelectric Field-Effect Transistors: Analytical Approach

Toprasertpong

Takenaka

Takagi

2022

IEEE Trans. Electron Devices

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A memory window of ferroelectric field-effect transistors (FeFETs), defined as a separation of the HIGHstate and the LOW-state threshold voltages, is an important measure of the FeFET memory characteristics. In this study, we theoretically investigate the relation between the FeFET memory window and the P-E hysteresis loop of the ferroelectric gate insulator, and derive a compact model explicitly described by material parameters. It is found that the memory window is linearly proportional to the ferroelectric polarization for the small polarization regime, and converges to the limit value of 2×coercive field× thickness when the remanent polarization is much larger than permittivity×coercive field. We discuss additional factors that possibly influence the memory window in actual devices such as the existence of interlayer (no direct impact), interface charges (invalidity of linear superposition between the ferroelectric and charge-trapping hysteresis), and minor-loop operation (behavior equivalent to the generation of interface charges).

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Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics

Cited by 24 publications

References 32 publications

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Ultralow Subthreshold Swing of a MOSFET Caused by Ferroelectric Polarization Reversal of Hf_0.5Zr_0.5O₂ Thin Films

Memory Window in Ferroelectric Field-Effect Transistors: Analytical Approach

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Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics

Cited by 24 publications

References 32 publications

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Ultralow Subthreshold Swing of a MOSFET Caused by Ferroelectric Polarization Reversal of Hf0.5Zr0.5O2 Thin Films

Memory Window in Ferroelectric Field-Effect Transistors: Analytical Approach

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Ultralow Subthreshold Swing of a MOSFET Caused by Ferroelectric Polarization Reversal of Hf_0.5Zr_0.5O₂ Thin Films