Compact Modeling of Weak Inversion Generation Transients in SOI MOSFETs

Abstract

Generation-type drain current transients in advanced ͑down to 50 nm gate length͒ floating-body, partially depleted silicon on insulator ͑SOI͒ metal oxide semiconductor field effect transistors ͑MOSFETs͒ are investigated by 2D numerical simulation in weak inversion operation. An original compact analytical model is derived for the pure transient weak inversion operation and validated on both elementary and realistic 2D structures. The proposed subthreshold transient compact model allows accurate prediction of the influence of the generation lifetime, surface velocity ͑or interface state density͒, oxide thickness, and substrate doping on the floating-body-related transient behavior and duration, which is essential for advanced transistor optimization and subsequent circuit applications. Moreover, our model is a unique, robust tool for the electrical characterization of submicrometer SOI transistors because it allows the carrier lifetime extraction independently of the channel carrier mobility and device effective gate length. Finally, the model is successfully used in high-temperature operation for drain current transient prediction and generation lifetime extraction.

Impact of Halo Implantation on the Lifetime Assessment in Partially Depleted SOI Transistors

“…Several carrier generation lifetime measurement methods [6][7][8][9][10] consist in applying a step voltage at one of the gates and observing the transient drain current due to the floating body nature of the partially depleted devices [11][12].…”

“…For most measurement methods long channel devices are usually employed, because in short channel transistors the source/drain junction contribution results in a reduction of the drain current transients, causing a decrease of the extracted generation lifetime [9].…”

Reliability performance characterization of SOI FinFETs

“…An analysis of the drain current (I D ) transients after switching "on" or "off" the front gate voltage, has been used to assess the quality of the starting material, process-induced defects or contamination [6][7][8]. As there is no substrate current to quickly adjust the majority carrier density, equilibrium has to be reached through generationrecombination processes.…”

A Study on Characteristics of Wet Oxide Gate and Nitride Oxide Gate for Fabrication of NMOSFET

“…Device structures, device operation, and circuit design to obtain high speed under low supply voltage become more important.In order not to lose operation speed by reducing power supply voltage, threshold voltage should be reduced. The main subject in the low voltage, low power technology is scaling of device dimensions to deep submicron regime with high performance and good short channel immunity [5]. Hence, as the device dimension penetrates into the sub-0.1㎛ regime, the control of both threshold voltage and source drain punch through becomes the most important factors in designing low voltage/low power device.…”