Compact PUF Design With Systematic Biases Mitigation on Xilinx FPGAs

Abstract

Physical unclonable functions (PUFs) are a strong and secure root source for identification and authentication applications. PUFs are especially valuable in FPGA-based systems because FPGA designs are vulnerable to intellectual property (IP) thefts and cloning, which PUFs protect against by generating random but device-specific bitstrings. Theoretically, the randomness of PUFs originates from variations in the manufacturing process. PUFs should be free of deterministic variation owing to the systematic bias among all chips of the same model. Correspondingly, one of the major challenges for FPGA-based PUFs is the difficulty of avoiding systematic bias between nominally matched delays in competing paths. In this paper, a deep investigation into the LUT structure on a Xilinx FPGA was conducted. Based on the investigation findings, a compact PUF design based on programmable look-up table paths is proposed. The proposed intertwined structure and the novel 2-phase, 2-pass scheme significantly reduced the impact of systematic biases in the Xilinx FPGA LUT. The proposed PUFs exploit random variations in LUTs, thus exhibiting very good uniformity and uniqueness among the generated bitstrings.

Design and implementation of IDELAY-RO PUF in Xilinx ZYNQ PSoCs

“…PDL-PUF utilizes combinations of different LUT and path selections in an FPGA to construct three inverters in a single slice to form a ring oscillator [24], [25], [26]. By changing the delay path to affect the RO oscillation frequency, a PUF is constructed [31]. Another technique called DD-PUF [27] relies on the relationship between the stop time of oscillation and the delay time of the circuit.…”

Security Analysis of Digital-Based Physically Unclonable Functions: Dataset Generation, Machine Learning Modeling, and Correlation Analysis

“…65K records with a 40-bit challenge and 1-bit response each were used to rigorously analyze RO PUF with an additional modulus process [3]. Hu et al [4] and Aghaie et al [5] investigated the impact of system characteristics on the vulnerability of PUFs to ML-based modeling attacks.…”

A Design Strategy to Improve Machine Learning Resiliency for Ring Oscillator Physically Unclonable Function

“…The response output was a comparison between two separate RO frequency measurements. To demonstrate the viability and performance of the MRO-PUF, two types of RO-PUFs were used as the base hardware components: PDL-RO-PUF [20] and IPD-RO-PUF [21]. Both RO-PUFs are feasible candidates for the proposed MRO-PUF, because their responses are generated based on a comparison between the measured frequencies of the embedded ROs.…”

“…This is a common challenge for most of the RO-PUF variants. [21] is an improved variant of PDL-RO-PUF that uses a novel IPD structure to replace the LUT stage in PDL-RO-PUF to minimize systematic bias. The IPD-RO and IPD inverter stages are shown in Figure 3 and 4, respectively.…”