Compact Spiking Neural Network Implementation in FPGA

Maya, Selene; Reynoso, Rocio; Torres, Cesar; Arias-Estrada, Miguel

doi:10.1007/3-540-44614-1_30

Cited by 17 publications

(14 citation statements)

References 3 publications

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“…The design requires 80 slices and 120 lookup tables (LUTs) for 10:1 implementation (10 synapses per neuron) of integrate-and-fire model. This is very efficient as compared to [1] which required 13 slices per synapse and 47 slices for summation. In [4] it is reported that 33 slices for a synapse and 63 slices for a neuron are required.…”

Section: Proposed Architecturementioning

confidence: 98%

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Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware

Ghani

McGinnity

Maguire

et al. 2006

2006 International Conference on Field Programmable Logic and Applications

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Section: Proposed Architecturementioning

confidence: 98%

“…Mathematically we can describe this behaviour as (1) This equation describes the effect on membrane potential u over time where τm is the membrane time constant in which voltage leaks away and a spike is generated when voltage u crosses the threshold.…”

Section: Integrate and Fire Modelmentioning

confidence: 99%

Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware

Ghani

McGinnity

Maguire

et al. 2006

2006 International Conference on Field Programmable Logic and Applications

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“…Existing hardware implementations are mainly categorised as FPGA and VLSI based implementations. FPGA based implementations are reported in [8]- [12]. VLSI based implementations are widely covered in [13]- [15].…”

Section: ( ) = +mentioning

confidence: 99%

Exploiting the Reconfigurability of Programmable Hardware for Neural Engineering

Ghani¹

2015

IJEEE

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The use of programmable devices leads to flexible and area-efficient implementation of biologically plausible neural entities such as synapses and neurons. However, the area constraints of reconfigurable devices such as the Field Programmable Gate Arrays (FPGAs) limit their use to rather small and already trained neural networks. This paper investigates and describes area-efficient spiking neural building blocks to implement integrate-and-fire (IF) and leaky integrate-and-fire (LIF) neuron models on reconfigurable hardware. It is demonstrated that an abstract behaviour of spiking neurons can be emulated for bit accurate implementation. In a linear comparison, 2×10 3 synapses and 1.2×10 3 fully parallel artificial spiking neurons can be implemented with the proposed building blocks and architectures. By using bigger devices with more logic elements such as Virtex-5, it is possible to fit almost 4.3×10 3 synapses and 2.5×10 3 neurons. The main contributions of this paper include area-efficient fully parallel architectures that exclude the use of embedded multipliers, area-efficient architecture for a leaky membrane, and compact implementation of neural cell which can be used for emulating large scale fully parallel spiking neural networks.

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“…Maya [9] proposes an implementation with a stochastic bit-streams [1], where the value of a synapse is represented with a pseudo-random pulse-stream. As in other publications, the synapse is separated from the membrane potential block.…”

Section: Related Workmentioning

confidence: 99%

A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation

Kaulmann

Dikmen

Rückert

2007

7th International Conference on Hybrid Intelligent Systems (HIS 2007)

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Compact Spiking Neural Network Implementation in FPGA

Cited by 17 publications

References 3 publications

Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware

Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware

Exploiting the Reconfigurability of Programmable Hardware for Neural Engineering

A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation

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