Compact Thermal Model for Vertical Nanowire Phase-Change Memory Cells

Chen, I-Ru; Pop, Eric

doi:10.1109/ted.2009.2021364

Cited by 22 publications

(16 citation statements)

References 18 publications

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“…Care must also be taken with the limiting cases W ≫ t ox (1-dimensional heat flow through underlying oxide) as opposed to d or W ≪ t ox (3dimensional spreading into oxide), the latter being the case for all nanotube, nanowire, and even graphene nanoribbon data [90] typically available. Finally, the thermal boundary resistance (TBR) at the interfaces between the devices and its environment can also be a limiting factor, as is the case with nanotubes [30,91], phase-change memory devices [92,93], and to some extent graphene transistors [94,95]. The TBR in the latter case is approximately equivalent to the thermal resistance of 20-50 nm SiO 2 at room temperature, and of relatively little contribution to the commonly used graphene samples on 300 nm SiO 2 .…”

Section: Steady-state Thermal Resistancementioning

confidence: 99%

Energy dissipation and transport in nanoscale devices

2010

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Understanding energy dissipation and transport in nanoscale structures is of great importance for the design of energy-efficient circuits and energy-conversion systems. This is also a rich domain for fundamental discoveries at the intersection of electron, lattice (phonon), and optical (photon) interactions. This review presents recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures. First, the landscape of power usage from nanoscale transistors (~10 -8 W) to massive data centers (~10 9 W) is surveyed. Then, focus is given to energy dissipation in nanoscale circuits, silicon transistors, carbon nanostructures, and semiconductor nanowires. Concepts of steady-state and transient thermal transport are also reviewed in the context of nanoscale devices with sub-nanosecond switching times. Finally, recent directions regarding energy transport are reviewed, including electrical and thermal conductivity of nanostructures, thermal rectification, and the role of ubiquitous material interfaces.

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Section: Steady-state Thermal Resistancementioning

confidence: 99%

Energy dissipation and transport in nanoscale devices

2010

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“…Experiments have shown [44][45][46] ), so adding TBR simply makes it a slightly poorer thermal conductor.…”

Section: Discussionmentioning

confidence: 99%

The Design of Rewritable Ultrahigh Density Scanning-Probe Phase-Change Memories

Wright

Wang

Shah

et al. 2011

IEEE Trans. Nanotechnology

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Abstract-A systematic design of practicable media suitable for re-writeable, ultra-high density (> 1Tbit/sq.in.), high data rate (> 1Mbit/s/tip) scanning probe phase-change memories is presented. The basic design requirements were met by a Si/TiN/GST/DLC structure, with properly tailored electrical and thermal conductivities. Various alternatives for providing re-writeability were investigated. In the first case amorphous marks were written into a crystalline starting phase and subsequently erased by re-crystallization, as in other already-established phasechange memory technologies. Results imply that this approach is also appropriate for probe-based memories. However, experimentally the successful writing of amorphous bits using scanning electrical probes has not been widely reported. In light of this a second approach has been studied, that of writing crystalline bits in an amorphous starting matrix, with subsequent erasure by re-amorphization. With conventional phase-change materials, such as continuous films of Ge 2 Sb 2 Te 5 , this approach invariably leads to the formation of a crystalline 'halo' surrounding the erased (re-amorphized) region, with severe adverse consequences on the achievable density. Suppression of the 'halo' was achieved using patterned media or slow-growth phase-change media, with the latter seemingly more viable.

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“…Apart from the typical mushroom cell geometry [2], the most common geometry variant is the vertical pillar structure [5,12,13], which may be typically fabricated using nanowires. Other methods to reduce programming currents include changes in electrode materials [14], doping of the active region [15], and the possible use of thermoelectric effects [16,17].…”

Section: Introductionmentioning

confidence: 99%

“…Vertical pillar structures [5,12,13], on the one hand, are reported to have smaller programming currents due to confined size dimensions. These vertical cells also feature a less abrupt transition between the low and the high resistance states, thus making it possible to also engineer multi-bit operations [20].…”

Section: Introductionmentioning

confidence: 99%

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Programming Current Reduction via Enhanced Asymmetry-Induced Thermoelectric Effects in Vertical Nanopillar Phase-Change Memory Cells

Bahl

Rajendran

Muralidharan

2015

IEEE Trans. Electron Devices

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Thermoelectric effects are envisioned to reduce programming currents in nanopillar phase change memory cells. However, due to the inherent symmetry in such a structure, the contribution due to thermoelectric effects on programming currents is minimal. In this work, we propose a hybrid phase change memory structure which incorporates a two-fold asymmetry specifically aimed to favorably enhance thermoelectric effects. The first asymmetry is introduced via an interface layer of low thermal conductivity and high negative Seebeck coefficient, such as, polycrystalline SiGe, between the bottom electrode contact and the active region comprising the phase change material. This results in an enhanced Peltier heating of the active material. The second one is introduced structurally via a taper that results in an angle dependent Thomson heating within the active region. Various device geometries are analyzed using 2D-axis-symmetric simulations to predict the effect on programming currents as well as for different thicknesses of the interface layer. A programming current reduction of up to 60% is predicted for specific cell geometries. Remarkably, we find that due to an interplay of Thomson cooling in the electrode and the asymmetric heating profile inside the active region, the predicted programming current reduction is resilient to fabrication variability.

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Compact Thermal Model for Vertical Nanowire Phase-Change Memory Cells

Cited by 22 publications

References 18 publications

Energy dissipation and transport in nanoscale devices

Energy dissipation and transport in nanoscale devices

The Design of Rewritable Ultrahigh Density Scanning-Probe Phase-Change Memories

Programming Current Reduction via Enhanced Asymmetry-Induced Thermoelectric Effects in Vertical Nanopillar Phase-Change Memory Cells

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