Compaction-based concurrent error detection for digital circuits

Almukhaizim, Sobeeh; Drineas, Petros; Makris, Yiorgos

doi:10.1016/j.mejo.2005.03.009

Cited by 6 publications

(4 citation statements)

References 15 publications

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“…So, even if faults occur on the fly (in the NSF block) their effects are not manifested before the next active clock edge when the circuit moves to a state that is different from the normal condition. 1 In this paper, we have taken a simple sequential circuit, shown in Fig. 5, for illustration of the theory.…”

Section: Circuit Modeling Under Bridging Faultsmentioning

confidence: 99%

“…15(d). The "satisfyall-0" operation is applied on this dominating OBDD which generates the set IP 0;dominating ¼ fv 1 …”

Section: Generation Of Exhaustive Set Of Fd-transitions For Feedback mentioning

confidence: 99%

“…are employed and advanced fault models are considered which comprise bridging faults, transition faults, delay faults, etc. [22,10,31,1]. In BIST, every time before powering up the circuit it is tested using on-chip pattern generator and response analyzer.…”

Section: Introductionmentioning

confidence: 99%

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A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults

Biswal

Biswas

2015

Microelectronics Journal

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Section: Circuit Modeling Under Bridging Faultsmentioning

confidence: 99%

“…15(d). The "satisfyall-0" operation is applied on this dominating OBDD which generates the set IP 0;dominating ¼ fv 1 …”

Section: Generation Of Exhaustive Set Of Fd-transitions For Feedback mentioning

confidence: 99%

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A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults

Biswal

Biswas

2015

Microelectronics Journal

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“…On the other hand, the introduction of Variable Latency Functional Units (VLFUs) has broadened the design space with new implementation alternatives [11][12][13][14][25][26][27][28]. These FUs are characterized by an aggressive reduction of the clock period at the expense of requiring a variable number of clock cycles to complete an operation, depending on the input data.…”

Section: Introductionmentioning

confidence: 99%

Improving circuit performance with multispeculative additive trees in high-level synthesis

Barrio¹,

Hermida²,

Memik³

et al. 2014

Microelectronics Journal

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Abstract-The recent introduction of Variable Latency Functional Units (VLFUs) has broadened the design space of High-LevelSynthesis (HLS). Nevertheless their use is restricted to only few operators in the datapaths because the number of cases to control grows exponentially. In this work an instance of VLFUs is described, and based on its structure, the average latency of tree structures is improved. Multispeculative Functional Units (MSFUs) are arithmetic Functional Units that operate using several predictors for the carry signal. In spite of utilizing more than a predictor, none or only one additional very short cycle is enough for producing the correct result in the majority of the cases. In this paper our proposal takes advantage of multispeculation in order to increase the performance of tree structures with a negligible area penalty. By judiciously introducing these structures into computation trees, it will only be necessary to predict the carry signals in certain selected nodes, thus minimizing the total number of predictions and the number of operations that can potentially mispredict. Hence, the average latency will be diminished and thus performance will be increased. Our experiments show that it is possible to improve 26% execution time. Furthermore, our flow outperforms previous approaches with Speculative FUs.

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Circuit Level Concurrent Error Detection in FSMs

Kehl

2013

J Electron Test

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Compaction-based concurrent error detection for digital circuits

Cited by 6 publications

References 15 publications

A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults

A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults

Improving circuit performance with multispeculative additive trees in high-level synthesis

Circuit Level Concurrent Error Detection in FSMs

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