Compaction of machining chips: Experiments and modeling

Analysis of Die Compaction of Chip Geometry through Porous Continuum Model‐Based Approach

“…Separate figures of the three individual chip used in the compaction test are presented in Figure 5b-d. A comparison between the Abbas et al [20] model and present model, as well as a comparison with experimental data, are illustrated in Figure 5b-d. The experimental data, represented by •, and the compaction behavior data predicted by the model of Abbas et al, [20] represented by ▴, were used to compare the predictions of the present model.…”

“…A comparison between the Abbas et al [20] model and present model, as well as a comparison with experimental data, are illustrated in Figure 5b-d. The experimental data, represented by •, and the compaction behavior data predicted by the model of Abbas et al, [20] represented by ▴, were used to compare the predictions of the present model. The prediction of the present model is shown by the curve in Figure 5b-d.…”

“…A viable method for simulating the compaction behavior of swarf is presented using a porous continuum model in modeling the and c) pure powder samples from Ab Kadir et al [11] d) Swarf with various lengths and e) the specimen based on swarf after die compaction under force control at a rate of 222.4 N s À1 from Abbas et al [20] Reproduced with permission. [11] 2017, Elsevier.…”

“…The compaction experimental data from Abbas et al [20] were adopted using chips of varying lengths at room temperature, as depicted in Figure 5a, where chip A had the longest length, while chip C had the shortest length with the same width and Relationship between densification rate (n) and Rdi*Vol/ (l_t*l_w) for each of chips A, B, and C, and powder. [16] Figure 4.…”

“…Chip A [20] Chip B [20] Chip C [20] Al6061 powder [16] l_t thickness. The predicted compressive axial stress-strain curves for the compaction tests were compared to the experimental data for the three types of chip.…”