Comparative Analysis for Performance Evaluation of Full Adders Using Reversible Logic Gates

Batish, Kirti; Pathak, Shruti; Gupta, Richa

doi:10.1109/icics.2018.00036

Cited by 7 publications

(4 citation statements)

References 7 publications

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“…This current dynamic power consumption, leakage power consumption, area, and delay find the most effective circuit to compare and analyze the 1-bit full adder circuit using reversible logic [13,17,18]. The proposed self-checking and self-healing of full adder circuits compared to the conventional circuit consumes low power and high speed.…”

Section: Literature Surveymentioning

confidence: 99%

RETRACTED ARTICLE: A Novel Adaptive Current Control Technique Based Modified MOS Current Mode Logic Circuits for Low Power and Area Efficient

Pradeep¹,

Rani²,

Kumar³

et al. 2021

Wireless Pers Commun

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MOS current mode logic (MCML) is one of the most promising logic functions to counteract power analysis attacks. The static power MCML standard cells are significantly higher than the static CMOS logic to achieve an equivalent function. As a result, using such logical patterns is very limited in portable devices. The strange thing is that these devices are the most sensitive to physical attacks, which will benefit more people from passing MCML. The propose to overcome this limitation by significantly reducing the static power consumption of MCML-based full adder circuits. For this reason, current control by adaptive (ACCT) -MCML standard cell library is provided in each transistor cell suspension. The effect of sleep transistors on performance and area is negligible. In addition, the proposed difference library is compatible with Micro wind tools. The integrated real-time digital signal processing application, where the drive current must be high. The conventional design will have a low-efficiency supply voltage with low capacitance; even when operating, the circuit speed will be faster, and the delay will be high. So the proposed 14 T full adder based integrated circuit and adder are based on ACCT, which High power consumption, which has become an essential standard operation for the design of energy-efficient dedicated circuits, has become the primary function and compact device design, possible output. The coefficient plays a significant role in planning energy-saving processors and determining processor performance. Especially, the switching behavior is to diminish the power consumption of the design MCML full ladder logic. However, the performance of the circuit is less than the full adder binary logic. The proposed circuit's correctness and effectiveness are verified by Micro wind with a proposed MCML process of 0.13 μm and a power supply voltage of 4.2 V.

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Section: Literature Surveymentioning

confidence: 99%

RETRACTED ARTICLE: A Novel Adaptive Current Control Technique Based Modified MOS Current Mode Logic Circuits for Low Power and Area Efficient

Pradeep¹,

Rani²,

Kumar³

et al. 2021

Wireless Pers Commun

View full text Add to dashboard Cite

show abstract

“…The product is then generated by adding the output from the previous stage with the carry form the previous column using a single fast adder in the final step. One 7:3 counters is used each stage, which reduces hardware requirements and significantly reduces power consumption owing to enhanced localization [17].…”

Section: IIImentioning

confidence: 99%

“…LIMITATIONS OF EXISTING SOLUTIONS As the circuit operation and the circuit complexity increases then the overall delay of the design circuit will also increase so which will result in the higher delay of the designed circuit. Due to the complex structure of existing solution multiplier circuit consume more power during the circuit operation [20].…”

Section: IVmentioning

confidence: 99%

Design Wallace Tree Multiplier Using Reversible Gates

Kishore,

Prakash,

Sachin

et al. 2024

IJRASET

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Multipliers are essential components in digital circuit design. They have wide spread applications in digital signal processing and communication systems. Circuit designers in VLSI design seek compact, small scale circuits with low power consumption and minimal delay. The Wallace tree multiplier is an advanced version of tree based multipliers. Numerous algorithms have been developed to create the fastest multipliers, and the Wallace tree multiplier is one such example. It utilizes reversible compressors, full adders, and half adders. The results demonstrate that the Wallace tree multiplier using reversible gates outperforms traditional multipliers in terms of power dissipation and delay, with values of 0.027W and 29.327nS respectively.

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“…The RTL investigation was completed with RTL compiler 14.01 by Rhythm for Power, Region and Postponement at 90nm and 45nm innovation for both quick and moderate library. [3] G. Singh, et.al. Developing nanoscale processing structure quantum-dab cell automata (QCA) is advancing as a conceivable trade for integral metal-oxide-semiconductor innovation in not so distant future.…”

Section: _______________________________________________________________________________________mentioning

confidence: 99%

Survey on Fault Tolerance Startgies for Advance Microelectronics Chip

Shekhar¹

2019

IJRITCC

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In the complex advance microelectronics based system, handling units are managing gadgets of littler size, which are delicate to the transient faults. A framework should be fabricated that will perceive the presence of faults and fuses strategies to will endure these faults without troublesome the typical activity A transient fault happens in a circuit caused by the electromagnetic commotions, astronomical beams, crosstalk and power supply clamor. It is extremely hard to recognize these faults amid disconnected testing. Subsequently a region effective fault tolerant full adder for testing and fixing of transient and changeless faults happened in single and multi-net is proposed. Furthermore, the proposed design can likewise identify and fix perpetual faults. This structure acquires much lower equipment overheads with respect to the conventional equipment design. In this paper, talk about various fault tolerant methodology for CMOS and ICs.

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Comparative Analysis for Performance Evaluation of Full Adders Using Reversible Logic Gates

Cited by 7 publications

References 7 publications

RETRACTED ARTICLE: A Novel Adaptive Current Control Technique Based Modified MOS Current Mode Logic Circuits for Low Power and Area Efficient

RETRACTED ARTICLE: A Novel Adaptive Current Control Technique Based Modified MOS Current Mode Logic Circuits for Low Power and Area Efficient

Design Wallace Tree Multiplier Using Reversible Gates

Survey on Fault Tolerance Startgies for Advance Microelectronics Chip

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