Comparative Analysis of Standard 9T SRAM with the Proposed Low-Power 9T SRAM

Singh, Balraj; Kumar, Mukesh; Ubhi, Jagpal Singh

doi:10.1007/978-981-13-2553-3_52

Cited by 4 publications

(3 citation statements)

References 7 publications

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“…Here the comparison has been made between the different parameter of the implemented circuit with the previously design circuit FD8T (Do Anh-Tuan et al, 2011), SEDF9T (Ming-Hsien Tu et al, 2012) and 9T SRAM (B. Singh et al, 2019).…”

Section: Resultsmentioning

confidence: 99%

“…This single-ended disturb free 9T SRAM is designed using 65 nm technology. Singh et al (2019), proposed a 9T SRAM memory using cadence tool at 45nm technology. This circuit is supposed to be divided into two parts: A sleep transistor connected with standard 6T SRAM memory cell through which the cell is grounded at the bottom available in the left side of the circuit.…”

Section: T Sram Cellmentioning

confidence: 99%

See 1 more Smart Citation

Design and Analysis of SRAM Cell for Smart Application

Praveen¹,

Singh²

2022

Journal of Computer Science

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In today's circuit technology, power consumption and savings are key concerns. The driving reasons behind these innovations are portable devices that require high throughput and low power dissipation, such as computers, phones, and Personal Digital Assistants (PDAs). In portable devices, reducing or decreasing IC dissipated power through design optimization is a big problem, and restricted battery lifespan places very severe restrictions on overall power usage. In this study SRAM circuit for smart applications has been investigated using various factors such as write, read, dynamic, static power with voltage and temperature. The power consumption analysis is the most essential criteria for memory design. Because data stability is a critical concern, affecting both the read and write operations. The implemented 9T SRAM in this study is more efficient than the other SRAM in terms of power usage. When compared with the existing SRAM circuits taken for comparison of different parameters, the proposed 9T SRAM, circuit uses less than 28.2% write power, while it uses about the same for read operation. The data retention voltage for both circuits is 0.29 V, which is utilized to store the data in the circuit. The 32 nm Bulk CMOS process technology from PTM files is used for designing and analysis.

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Section: Resultsmentioning

confidence: 99%

Section: T Sram Cellmentioning

confidence: 99%

Design and Analysis of SRAM Cell for Smart Application

Praveen¹,

Singh²

2022

Journal of Computer Science

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“…RBL is precharged by the VDD and WWL at low ('0'V). The crosscoupled inverter is separated from the outer interconnect, when WWL, WBL and WBLB is kept LOW and the latch is no intrusion effect [10]. RBL is discharge and remain at VDD at depend on the data in the cross coupled inverter.…”

Section: ░ 2 System Modelmentioning

confidence: 99%

Performance Analysis of 9T SRAM using 180nm, 90nm, 65nm, 32nm, 14nm CMOS Technologies

Praveen

Singh²

2022

IJEER

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The growing markets for low-power electronic devices energized by battery have created the need for smaller power-efficient chips to prevent frequent charging of the source. Nowadays the market capitalization of low-power appliances is expected to grow from USD 4.9 billion by 2022 to USD 7.9 billion by 2027 as per global forecast to 2027 published by markets. The main factor leading to growth of low power electronics market includes demand of energy saving components, miniaturization, and entry of IoT (internet of things) devices. In addition, increased investment by automotive OEM (Original Equipment Manufacturer) and governments to promote the adoption of electric vehicles is expected to create more market opportunities. In this digital era, memory components play a major role in power consumption and this incites the research interest these days. CMOS (Complementary Metal Oxide Semiconductor) technology is growing rapidly towards greater integration into a single chip, resulting to a decrease in chip sizes using less space. Speed and stability demand is also growing up. Combined chip density increases as downtime technology continues. Stability and reliability are an important issue for the static random access memory (SRAM) memory device. In this paper, the design and analysis of CMOS based 9T SRAM cell in a variety of technologies is presented. The main focus of this review paper is to analyze 9T SRAM to test performance on several CMOS technologies (180nm, 90nm, 65nm, 45nm, 32nm, 14nm) with the help of a predictable technology (PTM) file. The butterfly curve method is used to examine the consistency of the SRAM bit cell in terms of static noise margin (SNM). It is clearly shown in this paper that as it progresses from 180nm to 14nm the delay decreases with stability.

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A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era

Kumar

Tomar

2020

Wireless Pers Commun

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Comparative Analysis of Standard 9T SRAM with the Proposed Low-Power 9T SRAM

Cited by 4 publications

References 7 publications

Design and Analysis of SRAM Cell for Smart Application

Design and Analysis of SRAM Cell for Smart Application

Performance Analysis of 9T SRAM using 180nm, 90nm, 65nm, 32nm, 14nm CMOS Technologies

A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era

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