2022
DOI: 10.1016/j.jmmm.2022.169161
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Comparative analysis of STT and SOT based MRAMs for last level caches

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Cited by 30 publications
(17 citation statements)
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“…Endurance, the number of times the device can be switched before the failure occurs, is proportional to the ratio of time to failure to switch times. The state-of-the-art technique, [12], attempts to improve the write performance of STT-RAM memories. However, the main concern was to find a way to decrease the WER as much as possible.…”
Section: B Random Error Intensifying Write Error Ratementioning
confidence: 99%
See 2 more Smart Citations
“…Endurance, the number of times the device can be switched before the failure occurs, is proportional to the ratio of time to failure to switch times. The state-of-the-art technique, [12], attempts to improve the write performance of STT-RAM memories. However, the main concern was to find a way to decrease the WER as much as possible.…”
Section: B Random Error Intensifying Write Error Ratementioning
confidence: 99%
“…The state-of-the-art technique, [12], attempts to improve the write performance of STT-RAM memories. However, the main concern was to find a way to decrease the WER as much as possible.…”
Section: B Random Error Intensifying Write Error Ratementioning
confidence: 99%
See 1 more Smart Citation
“…However, the power and speed of spintronic devices is a significant impediment to their mainstream adoption in the currently used switching mechanisms, such as spin-transfer torque (STT) and spin-orbit torque (SOT). The main issues that still remain to be solved in STT switching technique are high power consumption (~130µW) and high latency (3-10ns) 4 . SOT induced switching on the other hand emerged as more promising than STT due to its high efficiency in terms of both latency (1-5ns) and power consumption (~35µW) at the cost of more area consumption 4 .…”
Section: Introductionmentioning
confidence: 99%
“…The main issues that still remain to be solved in STT switching technique are high power consumption (~130µW) and high latency (3-10ns) 4 . SOT induced switching on the other hand emerged as more promising than STT due to its high efficiency in terms of both latency (1-5ns) and power consumption (~35µW) at the cost of more area consumption 4 .…”
Section: Introductionmentioning
confidence: 99%