Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

Janković, Nebojša; Armstrong, G.A.

doi:10.1016/j.mejo.2004.04.007

Cited by 27 publications

(8 citation statements)

References 13 publications

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“…The electrical characteristics of the device were done by solving Poisson's equation and continuity equation numerically within the defined meshes of the device [21]. The electrical potential energy and electron band structure can be computed using Poisson's equation.…”

Section: Device Simulationmentioning

confidence: 99%

Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric Pocket (VESIMOS-DP)

Saad

Hamzah

Seng

et al. 2013

2013 Fifth International Conference on Computational Intelligence, Modelling and Simulation

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The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. The comparison between VESIMOS and VESIMOS-DP was done to show the advantages of incorporating dielectric pocket (DP) to the performance of the device. An improved stability of threshold voltage, VTH was found for VESIMOS-DP device of various DP size ranging from 20nm to 80nm. The stability is due to the reducing charge sharing effects between source and drain region. However, the presence of DP layer has introduced another potential barrier in addition to the delta p+ (δp+) triangular potential barrier. Thus, increased amount of gate voltage needed to overcome those barriers and allows the electrons to flow from source to drain. Moreover, the DP layer has suppressed the parasitic bipolar transistor effect (PBT) with higher breakdown voltage as compared to without DP layer. Hence, the incorporation of DP into VESIMOS has enhanced its performance and presents elevated characteristics for nano-electronics device.

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Section: Device Simulationmentioning

confidence: 99%

Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric Pocket (VESIMOS-DP)

Saad

Hamzah

Seng

et al. 2013

2013 Fifth International Conference on Computational Intelligence, Modelling and Simulation

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show abstract

“…It should be noted that the intermediary parameter β is only dependent on the MOSFETs lose many of beneficial properties that undoped DG MOSFETs, and therefore the use of heavily doped devices are limited [57].…”

Section: Ie Outline Of the Dissertationmentioning

confidence: 99%

Compact Modeling of Experimental n- and p-Channel FinFETs

Song

et al. 2010

IEEE Trans. Electron Devices

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“…Following [26], Jankovic et al [27] have modified ATLAS default model parameter beta and vsat.n by setting beta=1 and …”

Section: Simulationmentioning

confidence: 99%

A Subthreshold Swing Model for Symmetric Double-Gate (DG) MOSFETs with Vertical Gaussian Doping

Tiwari¹,

Jit²

2010

JSTS:Journal of Semiconductor Technology and Science

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Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

Cited by 27 publications

References 13 publications

Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric Pocket (VESIMOS-DP)

Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric Pocket (VESIMOS-DP)

Compact Modeling of Experimental n- and p-Channel FinFETs

A Subthreshold Swing Model for Symmetric Double-Gate (DG) MOSFETs with Vertical Gaussian Doping

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