Comparative Analysis of Vertically Stacked Nanosheet FET based SONOS Memory

Abstract

This work presents vertically stackedNanosheet Field-Effect Transistors based SONOS memory cell and highlights the effect of vertically stacking sheets on the memory performance. Thanks to the gate around structure, the Program and Erase operations are performed via F-N tunneling using faster (10 µs) and lower voltages (9 V and -8 V, respectively) due to the higher electric field across the tunneling oxide (Eox) compared to planar devices. Moreover, the results show that increasing the number of stacked nanosheets boosts the drain current but with a negligible effect on the memory window due to the same E ox .