Comparative evaluation of e-beam charge reducing processes

Abstract

ABSTRACFThe intrinsic registration capability of current E-Beam lithographic tools has to approach or even go below the 0.10 j.tm value (<X> + 3c, ). However the L:tual level to level overlay measurements are generally found above this limit as resist materials trap the electric charges: the electron beam is deflected by the electrostatic forces, resulting in misalignment and distortion of the delineated patterns. Large pattern displacements can be observed depending on the experimental conditions. This paper aims to compare various charge reducing processes when used under exactly the same conditions (20 keY industrial machine and trilevel resist structure). No system apears as a perfect solution. There are partial solutions, but none is simple and satisfying; this contributes to present the electron-beam lithography as a marginal technique for IC manufacturing. WHY AN RIE PROCESS?High volume IC fabrication is mainly based on optical lithography. It was predicted, a decade ago, that optical lithography would not allow for submicron manufacturing, but the contrary has been proven today: optical lithography will remain the prevailing high volume production technology for the coming years, at least down to the 0,25 p.m feature size mark. At the same time, 20-30 KeV electron beam direct writing occupies a key position as the highest resolution technique. As such, it is used for advance R&D evaluations of devices with reduced dimensions (16 and 256 Mbit DRAMS).The resist systems required for advanced direct writing applications must perform well in typical device fabrication steps such as plasma etching, metallization or ion implatation. While high resolution, sensitivity, chemical and thermal resistance are essential to these applications, electron beam resist users have to reach a compromise.The best compromise consists in trilayer resist systems, in spite of the complexity of the process steps resulting in a poor yield. According to today's literature, describing the 0.35-0.5 im design technology, an RIE. trilayer process (consisting respectively of a planarizing bottom layer, an intermediate oxygen plasma resistant layer and a thin top imaging layer), is the process generally selected. Furthermore, the trilayer resist process is required for electron-beam lithography because it is one of the best solutions for decreasing the proximity effects resulting from the electrons backscauered from the underlying substrate. THE CHARGE EFFECT PROBLEMSThe intrinsic registration capability of current E-Beam lithographic tools has to approach or even go below the 0.10 im value (<X> + 3s ). However the actual level to level overlay measurements are generally found above this limit as resist materials trap the electric charges: the electron beam is deflected by the electrostatic forces, resulting in misalignment and distortion of the delineated patterns. Large pattern displacements can be observed depending on the experimental conditions.It has been demonstrated that the beam deflection increases with the total layer thickness12...