Comparative study of CA-based PRPGs and LFSRs with phase shifters

Rajski, J.; Mrugalski, Grzegorz; Tyszer, Jerzy

doi:10.1109/vtest.1999.766671

Cited by 16 publications

(10 citation statements)

References 20 publications

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“…It is why these vectors may no longer be considered as pseudo-random ones, which adversely affects the fault coverage in digital CUTs with the STUMPS-type LBIST architecture [3] (pp. 177-181), [12,[34][35][36][37]. In addition, page 322 in [38] shows an example to demonstrate that test vector sequences generated by an I-type LFSR and feeding parallel inputs of a circuit tested in the test-per-clock mode shall be incapable of detecting some faults in the digital circuit under test.…”

Section: Examplementioning

confidence: 99%

“…Likewise, subsequent vectors appearing at outputs of that register are also gradually shifted by only one bit (except for the bit number 0). These properties indicate a strong correlation both between binary sequences and between subsequent vectors appearing at outputs of the LFSR register [10,12,35]. As a consequence, sequences of test vectors produced by such a register must not be considered as fully pseudo-random ones, both for the test-per-scan and test-per-clock testing strategies [10,40].…”

Section: Examplementioning

confidence: 99%

“…As mentioned before, not only the LFSR register can be applied as a PRPG with the LBIST arrangement and the STUMPS architecture, but linear registers of the CA or GLFSR can be used as well. The most frequent design option of the CA register is the one-dimensional Linear Hybrid Cellular Automata (LHCA) with null boundary conditions, made up of cells with the rules 90 and 150 [10,12,[41][42][43][44]. In a later part of this study, such a design option of the CA register shall be designated as LHCA 90/150.…”

Section: Examplementioning

confidence: 99%

“…[65][66][67][68][69][70][71][176][177], although Cellular Automata (CA) can also be used for these purposes [3] (pp. 72-75), [10][11][12][13]. Some specific solutions may also comprise other types of linear registers such as PRPG modules, for instance Galois Linear Feedback Shift Register (GLFSR) [14][15][16].…”

Section: Introductionmentioning

confidence: 99%

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A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

Garbolino

2021

Applied Sciences

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Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT‑LFSR‑TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed.

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Section: Examplementioning

confidence: 99%

Section: Examplementioning

confidence: 99%

Section: Examplementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

Garbolino

2021

Applied Sciences

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“…The WRVG (Fig. 21) is implemented using a 32-b maximal-length ring generator [23], [24] followed by a phase-shifter network to ensure interbit phase independency [25], [26], and a logic based probability bias circuitry to generate weighted random vectors.…”

Section: Test Platform Implementation and Test Proceduresmentioning

confidence: 99%

Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability

Wong

Cheung

2013

IEEE Trans. VLSI Syst.

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Abstract-The key aspects of a good on-chip timing measurement platform are high measurement resolution, accuracy, and low area overhead. A measurement method based on transition probability (TP) has shown promising characteristics in all these areas. In this paper, the TP measurement method is examined through simulation to understand its apparent effectiveness and accuracy in measuring complex circuits. Timing uncertainties and logic glitch activities are considered in detail, and the effect of varying input vectors' probability distributions is analyzed to enable further accuracy improvements. Using a field-programmable gate array, the method is implemented and demonstrated as a modular on-chip test platform for testing complex arbitrary circuits. Practical circuits found in typical modular designs, including fixed/floating-point arithmetic and filter circuits, are chosen to evaluate the test platform. The resolution of the timing measurements ranges from 0.3 to 8.0 ps, and the measurement errors against reference measurements are found to be within 3.6%. The test platform can be applied to VLSI designs with minor area overhead, and provides designers with precise and accurate physical timing information of circuits.

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