Comparative Study of SiC Planar MOSFETs With Different p-Body Designs

Ni, Weijiang; Wang, Xiaoliang; Xu, Miaoling; Li, Mingshan; Chi, Feng; Xiao, Hao; Jiang, Lijuan; Li, Wei; Wang, Quan

doi:10.1109/ted.2020.2966775

Cited by 9 publications

(15 citation statements)

References 14 publications

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“…The doping concentration of the JFET region in both structures is set 1 × 10 17 cm -3 to reduce the R ON . The body region of SiC MOSFET should be well designed because it has great influence not only on device performance, but also on device reliability [26]. We adopted shielded planar topology in this study, which features a P+ body region under the channel region [27].…”

Section: Device Structures and Simulation Backgroundmentioning

confidence: 99%

“…In this study, we set the doping concentration of both pillar regions at 3.75 × 10 16 cm -3 , which achieves the highest Baliga's figure of merit (BFOM = BV 2 /R ON ). be well designed because it has great influence not only on device performance, but also on device reliability [26]. We adopted shielded planar topology in this study, which features a P+ body region under the channel region [27].…”

Section: Device Structures and Simulation Backgroundmentioning

confidence: 99%

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A Novel MOS-Channel Diode Embedded in a SiC Superjunction MOSFET for Enhanced Switching Performance and Superior Short Circuit Ruggedness

Yoon

Kim

2021

Electronics

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In this study, a novel MOS-channel diode embedded in a SiC superjunction MOSFET (MCD SJ-MOSFET) is proposed and analyzed by means of numerical TCAD simulations. Owing to the electric field shielding effect of the P+ body and the P-pillar, the channel diode oxide thickness (tco) of MCD can be set to very thin while achieving a low maximum oxide electric field (EMOX) under 3 MV/cm. Therefore, the turn-on voltage (VF) of the proposed structure was 1.43 V, deactivating the parasitic PIN body diode. Compared with the SJ-MOSFET, the reverse recovery time (trr) and the reverse recovery charge (Qrr) were improved by 43% and 59%, respectively. Although there is a slight increase in specific on-resistance (RON), the MCD SJ-MOSFET shows very low input capacitance (CISS) and gate to drain capacitance (CGD) due to the reduced active gate. Therefore, significantly improved figures of merit RON × CGD by a factor of 4.3 are achieved compared to SJ-MOSFET. As a result, the proposed structure reduced the switching time as well as the switching energy loss (ESW). Moreover, electro-thermal simulation results show that the MCD SJ-MOSFET has a short circuit withstand time (tSC) more than twice that of the SJ-MOSFET at various DC bus voltages (400 and 600 V).

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Section: Device Structures and Simulation Backgroundmentioning

confidence: 99%

Section: Device Structures and Simulation Backgroundmentioning

confidence: 99%

A Novel MOS-Channel Diode Embedded in a SiC Superjunction MOSFET for Enhanced Switching Performance and Superior Short Circuit Ruggedness

Yoon

Kim

2021

Electronics

View full text Add to dashboard Cite

show abstract

“…7) Therefore, it is desirable to lower the gate-drain charge (Q GD ) of devices for greater efficiency of power. [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23] One method to lower the Q GD is to form a p-type floating well at the center of the junction FET (JFET) region. Devices with a floating well have lower Q GD than those with a conventional structure.…”

Section: Introductionmentioning

confidence: 99%

1.2 kV SiC MOSFETs with tapered buffer oxide for the suppression of the electric field crowding effect

Yoon,

Kim,

Kim

et al. 2023

Jpn. J. Appl. Phys.

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1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with buffered oxide, which are developed to reduce the gate-drain charge (QGD), have the problem that the electric field is crowded at the corners of the buffered oxide. In this paper, 1.2 kV SiC MOSFETs with tapered buffer oxide are proposed to suppress the electric field crowding effect. The device with tapered buffer oxide having an angle of 40° demonstrates maximum electric field at the gate oxide in the off-state (Eox,max) of 1.87 MV/cm, achieving a 13.4 % reduction compared to the device with conventional structure. Additionally, it is verified that the output characteristics of 1.2 kV SiC MOSFETs can be improved by applying tapered buffer oxide. This is because the junction field effect transistor (JFET) region can be designed with high concentration through the suppression of the electric field of the tapered buffer oxide.

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“…For the above two structures, the Depletion Layer Capacitance (C DL ) is reduced due to a reduced gate-to-drain overlap, as a result, C gd is decreased. To further reduce C gd , Weijiang Ni, et al [10] proposed a thick central gate Oxide and buffered gate MOS-FET (TCOX-MOS), as shown in Figure 1c. Although the C DL value of TCOX-MOS is almost the same as that of BG-MOS, the Insulation Layer Capacitance (C IL ) is greatly reduced due to a thick oxide layer under the central gate.…”

Section: Introductionmentioning

confidence: 99%

“…To further reduce C gd , Weijiang Ni, et al. [10] proposed a thick central gate Oxide and buffered gate MOSFET (TCOX‐MOS), as shown in Figure 1c. Although the C DL value of TCOX‐MOS is almost the same as that of BG‐MOS, the Insulation Layer Capacitance (C IL ) is greatly reduced due to a thick oxide layer under the central gate.…”

Section: Introductionmentioning

confidence: 99%

1.2 kV 4H‐SiC planar power MOSFETs with a low‐K dielectric in central gate

Liu

et al. 2022

IET Circuits, Devices & Syst

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A 1.2 kV 4H-SiC planar power MOSFET with a low-K dielectric in central gate (LK-MOS) is proposed in this paper. The LK-MOS features a P+ shielding region and a thick low-K dielectric layer under the central gate. The insulation layer capacitance is reduced by the thick low-K dielectric, while the depletion layer capacitance is decreased due to the reduced gate-to-drain overlap. The LK-MOS is demonstrated to have 97.8%, 70.6%, and 52.2% lower HF-FOM (R on � C gd ), and 98.9%, 97.4%, and 69.4% lower HF-FOM (R on � Q gd ), when compared with that of the conventional MOSFET (C-MOS), Buffered-Gate MOSFET (BG-MOS) and Thick Central Oxide MOSFET (TCOX-MOS), respectively. Besides, the LK-MOS can also have 16.8%, 5.9% lower C gs , and 19.9%, 12.4% lower Q gs compared with that of BG-MOS and TCOX-MOS.

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Comparative Study of SiC Planar MOSFETs With Different p-Body Designs

Cited by 9 publications

References 14 publications

A Novel MOS-Channel Diode Embedded in a SiC Superjunction MOSFET for Enhanced Switching Performance and Superior Short Circuit Ruggedness

A Novel MOS-Channel Diode Embedded in a SiC Superjunction MOSFET for Enhanced Switching Performance and Superior Short Circuit Ruggedness

1.2 kV SiC MOSFETs with tapered buffer oxide for the suppression of the electric field crowding effect

1.2 kV 4H‐SiC planar power MOSFETs with a low‐K dielectric in central gate

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