Comparative Study on Mechanical and Thermal Performance of eWLB, M-Series™ and Fan-Out Chip Last Packages

Shih, Meng-Kai; Chen, Ryan; Chen, PeterBS; Lee, Ying-Chih; Chen, KarenYU; Hu, Ian; Chen, Tang-Yuan; Tsai, Lung Chang; Chen, Eatice; Tsai, Eddie; Tarng, David; Hung, Chih-Pin

doi:10.1109/ectc.2018.00252

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Chip-last or Rdl-first Process1

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Cited by 6 publications

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“…For other chip-last or RDL-first potential applications, see Refs. [93][94][95][96][97][98][99][100][101][102][103].…”

Section: Chip-last or Rdl-first Processmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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“…For other chip-last or RDL-first potential applications, see Refs. [93][94][95][96][97][98][99][100][101][102][103].…”

Section: Chip-last or Rdl-first Processmentioning

confidence: 99%