Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Abstract

Abstract-Power consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous networkon-chip implementations, optimized for a number of SoC designs. We adapted the COSI-2.0 framework with ORION 2.0 router and wire models for synchronous network generation. Our own tool, ANetGen, specifies the asynchronous network by determining the topology with simulated-annealing and router locations with force-directed placement. It uses energy and delay models from our 65 nm bundled-data router design. SystemC simulations varied traffic burstiness using the self-similar b-model. Results show that the asynchronous network provided lower median and maximum message latency, especially under bursty traffic, and used far less router energy with a slight overhead for the interrouter wires.

Design of an Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs

“…For these experiments, we assume hard IP blocks which have fixed dimensions and network adapter ports. This is in contrast to earlier work [1] which assumed soft-IP. In an actual design flow, the router placement our tool generates will provide input to the hierarchical placer, or floorplacer [40] that will legalize the placement of cells and macros composing each core.…”

“…COSI configures its router models to have weighted arbitration based on expected flow-specific traffic volume. While in some circumstances this may be desirable, it caused extremely long latencies for certain traffic flows, as can be seen in some previous results [1]. For this paper, we changed the switch arbitration such that the incoming packet waiting the longest is chosen for output from among the other contending input packets.…”

“…A more detailed schematic of the switch and merge modules can be found in previous work [1]. All of the circuits were designed with the static, regular V th , Artisan cell library on IBM's 65 nm 10 sf process except the MUTEX element in the merge module.…”

Link pipelining strategies for an application-specific asynchronous NoC

“…The network then empties that buffer as quickly as possible. More details on the traffic generator, simulator, and models are described in [21].…”

“…We integrated these two strategies within a tool that generates the network topology and placement, called ANetGen [21]. This tool searches for a network solution with the best power and latency characteristics, and generates a topology, floorplan, and SystemC simulator for the network.…”