Link pipelining strategies for an application-specific asynchronous NoC

Abstract

Wire latency across the links of a NoC can limit throughput, especially in deep submicron technology. Stateful pipeline buffers added to long links allow a higher clock rate, but this wastes resources on links needing only low bandwidth. In asynchronous (clockless) NoCs, link pipelining can be done to only those that will benefit from both increased throughput and buffering capacity, and is especially useful in heterogeneous embedded SoCs. We evaluate two strategies that determine where link pipeline buffers should be placed in the topology. The first compares available link bandwidth, based on physical wirelength, to the throughput needed by each source-to-destination path, for each link. The second adds buffers to a link such that its bandwidth is at least equal to the throughput of a core's network adapter. These strategies were integrated into our network optimization tool for an application-specific SoC. Simulations were based on its expected traffic patterns, floorplan-derived wirelength, and uses self-similar traffic generation for more realistic behavior. Results show improved large-message network latency and output buffer delay of the network adapter. There was a slight power increase with the addition of pipeline buffers, but our proposal is a complexity-effective improvement by the power*latency product metric. The results indicate the strategy of pipelining certain links provides more efficiency opposed to a ubiquitous addition of buffers.

An Efficient Algorithm for 3D NoC Architecture Optimization

“…The proposed algorithm has been tested on three benchmarks on different scales: DSP Filter with 6 cores [23], MPEG4 Decoder with 12 cores [24] and a realistic multimedia SoC benchmark (D 26 media) with 26 cores [22]. The architecture is designed on to 3 layers in 3D, and the maximum number of vertical links, N max ill = 25.…”

SAS: Source Asynchronous Signaling Protocol for Asynchronous Handshake Communication Free from Wire Delay Overhead

“…In order to put wave pipelining and signal integrity issues in perspective, consider our highest frequency network-onchip design operating at 2.6 GHz in a 65nm process [13]. The delay in picoseconds of well managed interconnect for this process is modeled with the linear regression equation len/10 + 16, were len is the wire length in microns [14], [15].…”

Design of an Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs

“…The insertion of link pipeline buffers in an async NoC was explored and compared against a similarly-designed synchronous "elastic" network [22]. Asynchronous link pipelining strategies were explored for application-specific SoCs in [23]. A comparison between the asynchronous network ANOC, and the mesochronous clocked network DSPIN, was performed in [7].…”