Abstract-Latency insensitivity is a promising design paradigm in the nanometer era since it has potential benefits of increased modularity and robustness to variations. Synchronous elasticization is one approach (among others) of transforming an ordinary clocked circuit into a latency insensitive design. This paper presents practical considerations of elasticizing reconvergent fanouts. It also investigates the suitability of previously published as well as new join and fork implementations for usage in the elastic control network. We demonstrate that elasticization comes at a cost. Measurements of a MiniMIPS processor fabricated in a 0.5 µm node show that elasticization results in area and dynamic and idle power penalties of 29%, 13% and 58.3%, respectively, without any loss in performance. These measurements do not exploit the capability of pipeline bubbles that occur if one needs to have unpredictable interface latency, or to insert extra bubbles into a pipeline due to wire delays. We finally show the architectural performance advantage of eager over lazy protocols in the presence of bubbles in the MiniMIPS.

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Abstract-Implementation of low energy, low latency transmission line interconnects on a network-on-chip presents the circuit designer with a variety of structural design choices. This work presents a study of the comparative effects of changing the wire geometries on the latency, energy dissipated, area, and noise properties of the transmission lines. These results will aid the engineer in the design and performance analysis of the global interconnect and foster a quantitative understanding of the wave signaling properties in the RLC regime.Energy dissipation in wires has become a primary bottleneck for the continued scaling of future interconnect networks. Packet switching on high radix network topologies exacerbates this problem due to the energy and latency overhead contributed by switches and routers. Alternative network fabrics utilizing low latency, low energy buses have shown promise in circumventing this problem [1]. Transmission lines (TL) are possibly the most suitable building blocks for bus-based topologies since they provide fast, low energy long distance communication using present generation CMOS devices and techniques. Reliable on-chip implementation of TL interconnects requires substantial analysis and careful design, often with the help of complex full-wave field solvers. Characterization of transmission lines is a well studied subject [2] [3] [4]; however, a direct relation between the physical and geometric properties of a TL link design and its effectiveness as a communication medium is not available. This work aims at providing an insight into the various trade-offs between the performance of global RLC wires and their geometric properties. The case study presented here is intended to serve as a guide for link designers to better understand the available design choices supplemented with numerical data.RC representations of long wires are rendered inaccurate due to high frequency inductance effects. Electromagnetic field solvers are required for analyzing the behavior of transmission lines in order to include second order effects such as substrate coupling. Since accuracy trumps solution time in this study, a 3D full wave solver is employed for the analyses [5]. Scattering (S) parameters are extracted from the TL geometries for a frequency range of 100 MHz to 100 GHz and written to a Touchstone file for over 50 different transmission line structures. Transient analyses are performed on these extracted values in Synopsys HSPICE using CMOS drivers and loads. The back end of the line (BEOL) arrangement from the Global Foundries 65nm LPE process, complete with a hierarchical dielectric structure, low resistivity substrate and dense lower metal layers, is used as the guide to set up the simulation environment. Tab.