Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects

Copetti, T.; Balen, Tiago R.; Brum, E.; Aquistapace, Caroline Oliveira; Poehls, L. M. Bolzani

doi:10.1007/s10836-020-05869-2

Cited by 4 publications

(4 citation statements)

References 33 publications

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“…The magnitude of the leakage current is influenced by factors such as material quality, surface state density, and the manufacturing process. Its presence is detrimental for several reasons: Firstly, it directly adds to the power dissipation, elevating the static power consumption of the circuit [7]. Secondly, the heat generated from this power loss can raise the circuit temperature, potentially compromising the circuit's stability and reliability.…”

Section: Lower Power Consumptionmentioning

confidence: 99%

Advantages of FINFET over traditional CMOS: Reasons and implications

Shan

2023

TNS

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In the relentless march of technological advancement, the semiconductor industry remains at the forefront of innovation. Among the myriad breakthroughs, FinFET technology stands out as a recent focal point in research. Serving as an avant-garde semiconductor manufacturing process, FinFET plays a pivotal role in enhancing chip performance, diminishing power consumption, and minimizing component size. At its core, FinFET is a distinct type of field-effect transistor (FET) that utilizes a thin silicon fin as the conducting channel. This structure has revolutionized the way transistors are designed, offering remarkable control over the current flow through the channel. This control is achieved by wrapping a gate material around the three visible sides of the fin, which provides superior switching behavior and leakage reduction. Beyond its foundational principles, FinFETs inherent characteristics offer numerous advantages. For instance, the technology paves the way for more densely packed transistors, enabling more powerful yet compact integrated circuits. Moreover, its innovative design leads to more energy-efficient chips, which are crucial for todays demanding computing and electronic environments.

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Section: Lower Power Consumptionmentioning

confidence: 99%

Advantages of FINFET over traditional CMOS: Reasons and implications

Shan

2023

TNS

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“…Further exploration of SCs' impact: the previously discussed SCs can be further explored to improve HTD faults coverage. It is known that the industry uses voltage, time, and temperature during manufacturing tests [47] and that these SCs significantly impact the detection of functional ETD faults [11,53] in FinFET SRAM. Additionally, it has recently been shown through electrical simulations that increasing supply voltage and temperature improves the detection of random read HTD faults [54].…”

Section: Test Solutions Outlookmentioning

confidence: 99%

Hard-to-Detect Fault Analysis in FinFET SRAMs

Medeiros

Fieback

et al. 2021

IEEE Trans. VLSI Syst.

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Manufacturing defects can cause Hard-to-Detect (HTD) faults in FinFET SRAMs. Detection of these faults, such as random read outputs and out-of-spec parametric deviations, is essential when testing FinFET SRAMs. Undetected HTD faults result in test escapes, which lead to early in-field failures. This paper presents a detailed analysis of HTD faults in FinFET SRAMs by exploring their sensitization and discussing solutions to improve HTD fault coverage during manufacturing testing. We first define the fault space for SRAMs and classify all faults in the space. Following this, we perform a systematic fault analysis based on injecting resistive defects in a memory cell, inspecting its behavior, and identifying HTD faults. Furthermore, we survey existing test solutions and discuss their HTD fault coverage and limitations. Based on our analysis, it is clear that no single test solution can fully detect all HTD faults, thus leading to test escapes. Hence, there is a need for new and more efficient test solutions. Improved detection of HTD faults could be achieved by using parametric test solutions, proposing solutions that cover yet-untargeted HTD faults, combining multiple test approaches into a single solution, and further exploring stress conditions. These new approaches would reduce test escapes and therefore improve the quality of FinFET SRAMs.

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“…These procedures are highly useful in memory design for reducing LPD. A persistent effort is made in device with circuit level to lessen the LPD and enhancing the logic circuits performance 8,9 …”

Section: Introductionmentioning

confidence: 99%

“…A persistent effort is made in device with circuit level to lessen the LPD and enhancing the logic circuits performance. 8,9 In structural level, an important revolution is the creation of FinFET transistors. The gate electrodes surround the tiny silicon body of this transistor.…”

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confidence: 99%

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

Sankranti,

Roji Marjorie

2023

Softw Pract Exp

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Static random‐access memory (SRAM) plays a vital component of digital systems. The main issue of SRAM cells is power leakage, which results in an increase in chip area. Therefore this manuscript proposes a shorted‐gate fin‐type field‐effect transistor based SRAM cell utilizing leakage control transistor technique (SGFinFETs‐SRAM‐LECTOR) for decreasing the leakage power delay by improving the static noise margins (SNMs) together with power delay product (PDP). Here, the SGFinFETs‐SRAM‐LECTOR is primarily applied to stacking enhancement for lessening the leakage power dissipation (LPD). Two more transistors are used in LECTOR for reducing the leakage current with delay, which is based on transistor stacking. LECTOR employs two more transistors that are connected in series between pull‐up and pull‐down networks that means additional SG FinFETs PMOS transistor insertions amongst the pull‐up network and output terminal, additional SG FinFETs NMOS transistor insertions amidst the pull down network and output terminal. These additional transistors can decrease the leakage current. The simulation of the proposed approach is implemented in HSPICE simulation tool. Some metrics are computed to validate the efficacy of the proposed approach. Finally, the proposed technique reaches 11.31%, 51.47%, 45.46% less read delay, 44.44%, 26.33%, 33.45% less write delay, 36.12%, 45.28%, 26.45% less read power, 34.5%, 33.56%, 22.41% less write power, 37.4%, 15.3%, 26.54% high read SNM, 33.67%, 35.8%,12.09% high write SNM when analyzed to the existing models.

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Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects

Cited by 4 publications

References 33 publications

Advantages of FINFET over traditional CMOS: Reasons and implications

Advantages of FINFET over traditional CMOS: Reasons and implications

Hard-to-Detect Fault Analysis in FinFET SRAMs

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

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