Comparison between positive and negative bias stress on N‐channel VDMOSFET transistors

Abstract

If you would like to write for this, or any other Emerald publication, then please use our Emerald for Authors service information about how to choose which publication to write for and submission guidelines are available for all. Please visit www.emeraldinsight.com/authors for more information. About Emerald www.emeraldinsight.comEmerald is a global publisher linking research and practice to the benefit of society. The company manages a portfolio of more than 290 journals and over 2,350 books and book series volumes, as well as providing an extensive range of online products and additional customer resources and services.Emerald is both COUNTER 4 and TRANSFER compliant. The organization is a partner of the Committee on Publication Ethics (COPE) and also works with Portico and the LOCKSS initiative for digital archive preservation. AbstractPurpose -The purpose of this paper is to apply a negative gate bias stress in order to study instabilities of threshold voltage in N-channel power vertical double-diffused metal-oxide-semiconductor field effect transistor (VDMOSFET). Variations in gate oxide trapped charge and interface trap densities are also calculated. Design/methodology/approach -A threshold voltage shift is detected; the oxide and interface trap densities were evaluated based on a direct measurement of the gate to source capacitance and conductance. Findings -Results presented show that the threshold voltage is decreasing with stress time, the capacitance and conductance curves are altered by applied stress, also the oxide traps and the interface traps densities are increasing with stress time. Originality/value -The positive bias stress seems to be more destructive in the case of the studied devices.

The comparison of gamma-radiation and electrical stress influences on oxide and interface defects in power VDMOSFET

“…1 and 2, re spec tively. As the thresh old volt age behav iour is caused by the de fects formed in the gate oxide and at the SiO 2 -Si in ter face dur ing the stress/anneal ing [23][24][25], the ob served dif fer ences point out to the con clu sion that the elec tri cal stress and the ir ra di ation prob a bly ini ti ate dif fer ent mech a nisms of de fects for ma tion in the gate ox ide and at the in ter face. This can be con firmed by fig.…”