Comparison of Different Design Alternatives for Hardware-in-the-Loop of Power Converters

Zamiri, Elyas; Sanchez, Alberto; Yushkova, Marina; Martínez-García, Maria Sofia; Castro, Ángel de

doi:10.3390/electronics10080926

Cited by 27 publications

(31 citation statements)

References 46 publications

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“…This is the minimum achievable dt with the proposed architecture based on fourth-order Runge-Kutta method, K-calculator blocks, semistep calculation during deadtimes, and the selected device. In the literature, some references can be found that reach smaller simulation steps for simple converters-such as boost and buck topologies-by using simpler methods like Euler [15,27]. However, this paper uses fourthorder Runge-Kutta which leads to a much more accurate model, as the order of the solver is O(dt 4 ), and fixes the detected issue not only for simple buck converters but to other topologies that are based on half-bridge modules.…”

Section: Synthesis Resultsmentioning

confidence: 99%

Modeling of Deadtime Events in Power Converters with Half-Bridge Modules for a Highly Accurate Hardware-in-the-Loop Fixed Point Implementation in FPGA

2021

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Hardware-in-the-loop (HIL) simulations of power converters must achieve a truthful representation in real time with simulation steps on the order of microseconds or tens of nanoseconds. The numerical solution for the differential equations that model the state of the converter can be calculated using the fourth-order Runge–Kutta method, which is notably more accurate than Euler methods. However, when the mathematical error due to the solver is drastically reduced, other sources of error arise. In the case of converters that use deadtimes to control the switches, such as any power converter including half-bridge modules, the inductor current reaching zero during deadtimes generates a model error large enough to offset the advantages of the Runge–Kutta method. A specific model is needed for such events. In this paper, an approximation is proposed, where the time step is divided into two semi-steps. This serves to recover the accuracy of the calculations at the expense of needing a division operation. A fixed-point implementation in VHDL is proposed, reusing a block along several calculation cycles to compute the needed parameters for the Runge–Kutta method. The implementation in a low-cost field-programmable gate arrays (FPGA) (Xilinx Artix-7) achieves an integration time of 1μs. The calculation errors are six orders of magnitude smaller for both capacitor voltage and inductor current for the worst case, the one where the current reaches zero during the deadtimes in 78% of the simulated cycles. The accuracy achieved with the proposed fixed point implementation is very close to that of 64-bit floating point and can operate in real time with a resolution of 1μs. Therefore, the results show that this approach is suitable for modeling converters based on half-bridge modules by using FPGAs. This solution is intended for easy integration into any HIL system, including commercial HIL systems, showing that its application even with relatively high integration steps (1μs) surpasses the results of techniques with even faster integration steps that do not take these events into account.

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Section: Synthesis Resultsmentioning

confidence: 99%

Modeling of Deadtime Events in Power Converters with Half-Bridge Modules for a Highly Accurate Hardware-in-the-Loop Fixed Point Implementation in FPGA

2021

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“…Buck converters are widely known and have been previously characterized elsewhere with and without losses [2,24,25]. To this end, different discretization methods [26] such as those of Euler [27,28], Tustin [28], zero-order hold (ZOH) [29] or Runge-Kutta [30] have been widely applied to solve the differential equations that determine the model's behavior.…”

Section: Hil Model Equationsmentioning

confidence: 99%

“…The hardware in the loop (HIL) technique has become a very popular approach for power electronics testing in recent years due to its safety and low-cost [1]. HIL allows the real-time emulation of the different parts of a system using digital hardware under non-invasive conditions [2,3]. HIL models reduce the cost of debugging, can avoid severe damages to real systems and finally reduce the overall test effort [4,5].…”

Section: Introductionmentioning

confidence: 99%

“…The use of floating-point NF could result in more complex and slower hardware with respect to the use of fixed-point NF, or be even less accurate [14]; however, on the other hand, it requires less user design effort [13]. Furthermore, the design software considered is of great importance, while software such as MATLAB/Simulink [15] or the use of high-level languages such as HLS [16] decrease the users' design effort, but they are not as efficient as using hard-coding like HDL languages [17,18], which generally ends up on slower and more complex hardware circuit simulations [2,[19][20][21]. Recently, some commercial HIL platforms such as Typhoon HIL [20], Opal-RT [22] or the National Instruments RIO family [23] have appeared to implement HIL models, however, these programs are not generally user-transparent and do not allow the designer to optimize the resulting model.…”

Section: Introductionmentioning

confidence: 99%

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Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx

Cirugeda-Roldán¹,

Martínez-García²,

Sanchez³

et al. 2021

Electronics

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Hardware in the loop is a widely used technique in power electronics, allowing to test and debug in real time (RT) at a low cost. In this context, field-programmable gate arrays (FPGAs) play an important role due to the high-speed requirements of RT simulations, in which area optimization is also crucial. Both characteristics, area and speed, are affected by the numerical formats (NFs) and their rounding modes. Regarding FPGAs, Xilinx is one of the largest manufacturers in the world, offering Vivado as its main design suite, but it was not until the release of Vivado 2020.2 that support for the IEEE NF libraries of VHDL-2008 was included. This work presents an exhaustive evaluation of the performance of Vivado 2020.2 in terms of area and speed using the native IEEE libraries of VHDL-2008 regarding NF. Results show that even though fixed-point NFs optimize area and speed, if a user prefers the use of floating-point NFs, with this new release, it can be synthesized—which could not be done in previous versions of Vivado. Although support for the native IEEE libraries of VHDL-2008 was included in Vivado 2020.2, it still lacks some issues regarding NF conversion during synthesis while support for simulation is not yet included.

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“…Among the recently strongly developed HiL systems, we will highlight: RTDS Technologies Inc. [12] (used, e.g., for simulation of Static VAR compensator (SVC) in a large power system [13]), Opal-RT Technologies [14] (used, e.g., for estimation of on-line parameters and current control of a six-phase induction machine [15]) and dSPACE [16] (used, e.g., for permanent magnet motors [17], and multilevel converters [18]). The FPGA-based design alternatives to HiL in power converters with different coding methods and numerical formats are compared in terms of area and speed in [19]. Another interesting approach is the proposed ultralow-latency HiL platform combining flexibility, accuracy and ease of use of state-of-the-art-simulation packages with the response speed of small powerhardware models [20].…”

Section: Introductionmentioning

confidence: 99%

Overview of Control Algorithm Verification Methods in Power Electronics Systems

et al. 2021

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The paper presents the existing verification methods for control algorithms in power electronics systems, including the application of model checking techniques. In the industry, the most frequently used verification methods are simulations and experiments; however, they have to be performed manually and do not give a 100% confidence that the system will operate correctly in all situations. Here we show the recent advancements in verification and performance assessment of power electronics systems with the usage of formal methods. Symbolic model checking can be used to achieve a guarantee that the system satisfies user-defined requirements, while statistical model checking combines simulation and statistical methods to gain statistically valid results that predict the behavior with high confidence. Both methods can be applied automatically before physical realization of the power electronics systems, so that any errors, incorrect assumptions or unforeseen situations are detected as early as possible. An additional functionality of verification with the use of formal methods is to check the converter operation in terms of reliability in various system operating conditions. It is possible to verify the distribution and uniformity of occurrence in time of the number of transistor switching, transistor conduction times for various current levels, etc. The information obtained in this way can be used to optimize control algorithms in terms of reliability in power electronics. The article provides an overview of various verification methods with an emphasis on statistical model checking. The basic functionalities of the methods, their construction, and their properties are indicated.

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Comparison of Different Design Alternatives for Hardware-in-the-Loop of Power Converters

Cited by 27 publications

References 46 publications

Modeling of Deadtime Events in Power Converters with Half-Bridge Modules for a Highly Accurate Hardware-in-the-Loop Fixed Point Implementation in FPGA

Modeling of Deadtime Events in Power Converters with Half-Bridge Modules for a Highly Accurate Hardware-in-the-Loop Fixed Point Implementation in FPGA

Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx

Overview of Control Algorithm Verification Methods in Power Electronics Systems

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