Comparison of doping profiles in capless annealed and dielectrically capped — Annealed ion implanted GaAs

Siu, D. P.; Immorlica, A.A.

doi:10.1007/bf02822722

Cited by 6 publications

(1 citation statement)

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“…Redistribution and broadening of the carrier concentration profile in GaAs implanted with Zn was similar to that implanted with S as was previously reported (2). Siu and Immorlica also reported on the effect of Si3N4 capping on the broadening of the pro- files in Se-and S-implanted GaAs wafers by comparing the profiles after capped and capless annealing (8). As well as electrical profiles, the broadening of the atomic concentration profile of implanted Zn was observed after capped annealing by SIMS analysis (9).…”

Section: Resultsmentioning

confidence: 93%

The Effect of Stress on the Redistribution of Implanted Impurities in GaAs

Kasahara¹,

Kato²,

Arai³

et al. 1983

J. Electrochem. Soc.

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The stress introduced by the difference in thermal expansion coefficients between an encapsulant and a substrate was found to affect the redistribution of implanted impurities during annealing. Compressive stress introduced by an SigN4 film on GaAs enhanced the diffusion of implanted Si, Se, and S. Diffusion constants of Si and Se increased exponentially with the increase in the film thickness in a thickness region less than 0.1 ~m. The diffusion mechanism was discussed and it was concluded that the change in the jump frequency of diffusing atoms was dominant in determining the effect of stress in the damaged implantation layer. Excess of carriers was also observed in Se-and S-implanted samples, while deficit in carriers was observed in Si-implanted samples when the samples were subsequently annealed with an Si3N4 film. ~mall logic swing is essential for achieving a GaAs logic integrated circuit, particularly in ennancementmode logic circuits, where logic swing in Schottky barrier FETes should be 0.7V at most and that in junction FET's 1.2V to avoid appreciable gate current. Channel layers of both FET's are usually formed by ion implantation directly into a semi-insulating ~ubstrate. Variation of the carrier concentration profile in the ion-implanted channel layer over the whole wafer is a most crucial problem for uniformity and reproducibility of the devices. Precisely controlled ion-implanted layers are required to achieve GaAs integrated circuits.ion implantation technology is advantageous, because it can, in principle, control the profile for the channel layer only by changing the implantation energy and ion .dose. The profile is predicted by the LSS range statistics (1). A damaged layer by ion implantation, however, has to be annealed at high temperature in order to remove radiation damage and to activate implanted impurities as donors or acceptors. Implanted impurities are redistributed by diffusion during postimplantation annealing at high temperature. The factors affecting the redistribution were discussed previously by Kasahara and Watanabe (2) and Yoder (3). Thermal stress during post-implantation annealing was pointed out to be one of the factors, and the example was shown in the case of Zn ion implantation into GaAs (2). The effect of the thermal stress on the redistribution of Cr in Cr-doped semi-insulating substrates was also reported (4, 5). However, it is not clear how the stress influenced the redistribution of implanted impurities in GaAs.In this paper, the effect of the external stress on the redistribution of implanted Si, Se, and S in GaAs is investigated by using a wafer with thermal stress introduced by the .difference in the thermal expansion coefficient between an encapsulant and GaAs. Following the descriptions of the experimental conditions and the results, we discuss variations in the diffusion constants of implanted Si and Se under a wide range of external stress conditions. Variations in the doping efficiency of the implanted impurities are also described briefly as a function of the...

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Section: Resultsmentioning

confidence: 93%