Comparison of fully depleted and partially depleted mode transistors for practical high-speed, low-power 0.35 μm CMOS/SIMOX circuits

Yoshino, Akira; Kumagai, K.; Hamatake, N.; Kurosawa, Susumu; Okumura, K.

doi:10.1109/soi.1994.514269

Cited by 5 publications

(2 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Such applications rely heavily on circuit blocks such as latches that allow operation such as pipelining and power-down techniques. This paper examines the metastability of CMOS latches based on partially depleted (PD) SOI devices (Yoshino et al 1993) with various body-connection topologies. The behaviour of the di erent is s topologies is analysed and compared using SOISPICE simulations and calibrated device models.…”

Section: Introductionmentioning

confidence: 99%

Metastability of SOI CMOS latches

Tretz¹,

Chuang²,

Terman³

et al. 1999

International Journal of Electronics

View full text Add to dashboard Cite

An analysis of the metastability of silicon-on-insulator (SOI) complementary metal-oxide± silicon (CMOS) latches is presented, using partially-depleted SOI devices with various body-connection topologies and an unbu ered latch. The metastability window, resolution time and time interval between the clock edge and the time t meta are evaluated as functions of power supply and the type of body-connection topology. Simulations using SOISPICE show improved metastability behaviour for SOI speci® c body-connection topologies.

show abstract

Section: Introductionmentioning

confidence: 99%

Metastability of SOI CMOS latches

Tretz¹,

Chuang²,

Terman³

et al. 1999

International Journal of Electronics

View full text Add to dashboard Cite

show abstract

“…Partially-depleted device offers threshold voltage control comparable to bulk silicon [ll] while maintaining other SO1 benefits such as reduced junction capacitance, a key attribute for low-power applications [12]. Partially-depleted device does suffer from degraded subthreshold slope and floating body effect.…”

Section: B ) Technologymentioning

confidence: 99%

TFSOI technology for portable wireless communication systems

Huang

Tseng²,

Monk³

et al.

Proceedings of CICC 97 - Custom Integrated Circuits Conference

View full text Add to dashboard Cite

Recent growth in the portable wireless communication market has driven semiconductor technologies toward voltage and power reduction. The reduced junction capacitance and near-ideal MOS device characteristics of SO1 provides an inherent advantage for low-voltage low-power applications. Substantial progress in applying SO1 technology for these applications has been demonstrated in recent years. The quest for a single chip system has also initiated work in developing high frequency and analog SO1 circuits. In this paper, the application of Thin-Film-Silicon-On-Insulator (TFSOI) technology for wireless communication systems will be reviewed and future development will be discussed.

show abstract