Comparison of High-Level Synthesis and Hardware Construction Tools

The article is devoted to the development of a proprietary CAD system designed for the design of various digital microelectronics devices. The presented works were carried out by VSFEU in cooperation with ROSELECTRONICS Holding. Cadence software was used to simulate a digital microprocessor based on SYNTACORE's 32-bit SCR1 core with the implementation of the IMC instruction set. The synthesis of the RTL model for testing was carried out in automatic mode and included a stage of testing for synthesizability and a stage of direct synthesis. The synthesis was carried out on the basis of standard library elements of the selected technology for the 130 nm process of the HHGRACE factory. For the created model, a test of the connection list (netlist) was performed, while the logical model was replaced by a list of circuits. Then the calculation of the power consumed by the circuit was carried out. At the end of the development, various tests aimed at verifying the correctness of the RTL code were carried out for the ready-made model - tests for compliance with specificity, tests for edge cases (corner case testing), tests based on applied tasks and algorithmic testing (real code testing), as well as tests for pico-high performance and throughput of switches and interfaces.

Technology of RTL product description model development in the development of CAD soft-ware and analytical complex

Shehovcov,

Plotnikov,

Zolnikov

et al. 2023

Design route and testing of RTL analog blocks of the CAD software and analytical complex

Shehovcov,

Stoyanov,

Skvortsova

et al. 2023

The article discusses the stages of development of domestic CAD designed for the design of various digital devices of microelectronics. The presented works were carried out by VGLTU together with ROSELECTRONICS Holding. An important process in the development of CAD is the design of analog RTL (Register Transfer Level) blocks that determine the logic of the device functioning at a low level. This development needs to build a design route and test RTL blocks, for the practical implementation of which the programming languages of the Verilog and SystemVerilog microcontrollers were used. At the beginning, the CAD testing route is described in detail with a detailed description of its stages. Then the cells of functional SF blocks were generated, and the algorithm of its generation was given. The distinctive features of the conducted analysis is the ability to conduct testing for analog blocks. At the end, various testing methods were used, including functional testing, performance testing at various loads and verification of compliance with specifications. Also, the simulation of the operation of the units at different operating frequencies and with changing parameters was carried out. In conclusion, we described the process of installing CAD on the developer's workstation, which is necessary for the correct use of the PCB in the Cadence environment.

Integrating the Calibre software product into the Cadence Virtuoso environment and increasing the intelligent properties of CAD IC design

Poluektov,

Shehovcov,

Skorkin

et al. 2023

The article discusses the technology for integrating Caliber into the Cadence Virtuoso environment and describes the impact of this integration on the productivity of engineers. The possibility of ensuring optimal interaction between developers and increasing the overall efficiency of the design team is considered, leading to end-to-end design optimization. The integration of Caliber and Cadence Virtuoso represents an important step in Electronic Design Development (EDA) and can solve a number of problems while improving the efficiency of the verification and analysis process. Here are a few aspects that demonstrate the need and benefits of such integration, data interoperability, ensuring that information received from Virtuoso can be used correctly and efficiently in Caliber and vice versa, automating the data transfer process and performing verification, speeding up all development cycles, verification can carry out, even in the early stages of design, smoother interaction between different teams using Virtuoso and Caliber. In the second part of the article, physical verification and extraction of the project is carried out using the graphical interface of the Mentor Graphics Caliber CAD system, where the topology is checked for compliance with the CTO (DRC check). For the DRC check of a project, check is performed using the Caliber application. Using Caliber in Cadence Virtuoso allows for more accurate verification of designed electronic circuits and microchips. Caliber provides deeper analysis of physical parameters such as layer compatibility, electrical and geometric rules, leading to the identification of potential problems earlier in development.