Comparison of InP/InGaAs DHBT distributed amplifiers as modulator drivers for 80-Gbit/s operation

Abstract

This paper compares three single-ended distributed amplifiers (DAs) realized in an in-house InP/InGaAs double heterojunction bipolar transistor technology featuring an f(ind t) and f(ind max) larger than 200 GHz. The amplifiers use five or eight gain cells with cascode configuration and emitter follower buffering. Although the technology is optimized for mixed-signal circuits for 80 Gbit/s and beyond, DA results could be achieved that demonstrate the suitability of this process for the realization of modulator drivers. The results are documented with scattering parameter, eye diagram, and power measurements. This includes amplifiers featuring a 3-dB bandwidth exceeding 80 GHz and a gain of over 10 dB. One of the amplifiers exhibits clear eyes at 80 Gbit/s with a gain of 14.5 dB and a voltage output swing of 2.4 V(ind pp) limited by the available digital input signal. This amplifier delivers an output power of 18 dBm (5.1 (V ind pp)) at 40 GHz and 1-dB compression. Two amplifiers offer a tunable gain peaking, which can be used to optimize circuit performance and to compensate losses in the circuit environment. The results show that, using our InP/InGaAs technology, an integration of high-speed mixed-signal circuits (e.g., multiplexers) and high-power modulator drivers on a single chip is feasible

The (R)evolution of Distributed Amplifiers: From Vacuum Tubes to Modern CMOS and GaN ICs

“…In order to improve the gain of the DA, multi-stage amplifiers are adopted as the gain stage [27], [36]- [39]. Bandwidth enhancement techniques [40], [41] can be employed to avoid bandwidth limitation by inter-stage parasitic capacitances.…”

“…An impressive bandwidth of 5-100 GHz with 5.5 dB average gain was achieved using a 0.1µm InP HEMT process. InP has been a popular process in implementation of extremely wideband DAs [5], [27], [74]- [82]. A performance summary of state-of-the-art InP DAs is presented in Table II.…”

A 40-Gb/s 4-Vpp Differential Modulator Driver in 90-nm CMOS

“…The supply voltage suggested by the foundry for the adopted 90-nm RF CMOS is 1.2 V (maximum up to ~ 1.5 V) to avoid transistor breakdown and ensure long-term reliability. The cascode configuration is often used to enhance the output voltage swing [6]- [7]. However, the gate bias of the CG stage is fixed in a typical cascode gain cell, and hence the transistor could encounter the breakdown situation if a large swing appears at the drain node of the cascode cell.…”

100-Gbit/s Full-ETDM Transmission Technologies

“…Here too, there are already promising results from previous work, but they have to be improved further. Table 3 shows some results achieved for 80 GBaud, measured on-chip [10], compared to the targets within HECTO for the driver amplifier module for 107 GBaud. Note that the achieved output voltage for 80 GBaud was limited by the available input power and power measurements indicated that considerably higher output voltage were possible.…”