Comparison of ionizing radiation effects in 0.18 and 0.25 /spl mu/m CMOS technologies for analog applications

Quadruple Well CMOS MAPS With Time-Invariant Processor Exposed to Ionizing Radiation and Neutrons

“…The observed change in the ENC may instead be ascribed to an increase of the flicker noise contribution from the same transistor, resulting from the increase in the border (or near-interfacial) trap density due to hole-trapping in the device gate oxide [17]. This is supported by literature data discussing -ray effects on low frequency noise in NMOS transistors belonging to the 180 nm node [18]. A different behavior, with a significant increase in the flicker noise due to charge trapping in the STI, was instead detected in devices belonging to the 130 nm CMOS node.…”

Total ionizing dose effects on the noise performances of a 0.13 /spl mu/m CMOS technology

“…The increase of noise is also very small. To this respect, 0.13 m PMOSFETs are less sensitive than 0.18 m devices from the same foundry [6], with a ratio between the value of at 10 Mrad dose and its pre-irradiation value of 1.1 (0.13 m PMOS) and 2.1 (0.18 m PMOS). This reduced noise sensitivity is likely to be associated to the thinner gate oxide and correlated to the reduced threshold voltage shift.…”

“…A test chip was designed and fabricated, including PMOS and NMOS devices with gate lengths of 0.13, 0.20, 0.35, 0.7, and 1 m and gate widths of 200, 600, and 1000 m. Devices with such a large are commonly used as front-end elements in readout systems for particle detectors, in order to achieve the best noise performances [8]. For comparison purposes, the paper reports data relevant to devices in a CMOS process from the previous generation, with a minimum gate length of 0.18 m (also manufactured by STMicroelectronics) [6]. The corresponding electrical gate oxide thickness is 4 nm and is about 8.8 fF/ m .…”

“…It was shown in [6] that the transconductance of both NMOS and PMOS in CMOS generations from 0.35 to 0.18 m is affected by irradiation to a very limited extent. A similar behavior is observed in the 0.13 m technology studied in this paper, except for NMOS devices with a channel length approaching the minimum feature size.…”

“…In previous CMOS generations, it was found to be one of the most sensitive parameters to ionizing radiation, and its behavior can be correlated to the threshold voltage shift [5]. In this work, the radiation hardness Manuscript featured by the 0.13 m process is evaluated by a comparison with data from previous CMOS generations [6]. This study is focused on applications to high density mixedsignal integrated circuits, where power dissipation is an important issue and critical devices in the analog processing section have to operate at low current density.…”