Comparison of OPC rules and common process windows for 130-nm features using binary and attenuated phase-shift masks

Reilly, Michael T.; Parker, Colin R.; Kvam, Karen; Socha, Robert; Dusa, Mircea V.

doi:10.1117/12.388959

Cited by 3 publications

(2 citation statements)

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“…These rules are generated by laboriously examining a multitude of features (under a wide range of OPC conditions), then manually choosing the assist feature and fme bias configuration which minimizes the CD offset between pitches and maximizes the common process window. 5 To complicate these rules further, they are a strong function of illumination condition6 and substrate reflectivity, so potentially a different set of rules is required for each critical process layer.…”

Section: Introductionmentioning

confidence: 99%

Calibration of ESCAP resist simulation parameters from consideration of printed CD pitch bias, CD measurement offset and wafer thermal history

Robertson¹,

Kang²,

Tye³

et al. 2002

SPIE Proceedings

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In this work an automated optimization routine is used to modify modeling parameters for a chemically amplified photoresist, with the goal of minimizing the error observed between lithography simulation and experimental results. It is shown that a basic tuning procedure modifying, optimizing only CD measurement offset and acid generation efficiency, improves the fit significantly. Further improvements can be made by optimization of the diffusiondeprotection kinetic parameters, in combination with the two aforementioned values. It is shown further improvement is observed if the actual temperature profile experienced in the postexposure bake process is considered and the temperature dependence of both the diffusion and the deprotection processes are optimized. This parameter values that result in this improvement infer a temporal offset in the start, and finish, ofdeprotection and acid diffusion.

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Section: Introductionmentioning

confidence: 99%

Calibration of ESCAP resist simulation parameters from consideration of printed CD pitch bias, CD measurement offset and wafer thermal history

Robertson¹,

Kang²,

Tye³

et al. 2002

SPIE Proceedings

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show abstract

“…1 However, the large bias that resulted from using aggressive off-axis illumination (OAI) presents a dilemma for two lithography options. The first is for users of model based OPC who require a mechanism for lowering the cost of ownership of masks with assist features.…”

Section: Introductionmentioning

confidence: 99%

Maximizing common process latitude by integrated process development for 130-nm lithography

Reilly¹,

Parker²,

Fischer³

et al. 2002

SPIE Proceedings

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Maximized inherent common process latitude of 130 nm line/space features through pitch is demonstrated in this work. It is shown that the principle method for doing so is by reducing the through pitch, or proximity, bias. The effects that formulation, illumination optics and mask error have on proximity bias are studied. Formulations exhibit a wide range of bias that does not necessarily depend upon activation energy or process temperatures. Optical settings for inner and outer sigma for both annular and quadrupole illumination, likewise, have a demonstrable effect on the proximity bias. Larger, tighter annuli or poles produce larger bias, while lower settings incur a loss of resolution. Either effect limits the common latitude so a balance is struck between them. Additionally, while the effect of outer sigma is obvious in the data, the inner sigma effect is not observed until data are corrected for mask error and the mask error factor. The proximity bias ranges between approximately 10 and 80 nm, depending upon the combination of conditions. Sub-resolution assist features (scattering bars) are specifically excluded from use in this experiment.

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Performance improvement in gate level lithography using resolution enhancement techniques

Chua

Tay

Quan

et al. 2004

Microelectronic Engineering

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Comparison of OPC rules and common process windows for 130-nm features using binary and attenuated phase-shift masks

Cited by 3 publications

References 0 publications

Calibration of ESCAP resist simulation parameters from consideration of printed CD pitch bias, CD measurement offset and wafer thermal history

Calibration of ESCAP resist simulation parameters from consideration of printed CD pitch bias, CD measurement offset and wafer thermal history

Maximizing common process latitude by integrated process development for 130-nm lithography

Performance improvement in gate level lithography using resolution enhancement techniques

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