Comparison of p-i-n and n-i-n carbon nanotube FETs regarding high-frequency performance

An efficient structure for T-CNTFETs with intrinsic-n-doped impurity distribution pattern in drain region

“…To study the high frequency and RF behavior of nano-scale transistors, obtaining the intrinsic cut-off frequency is mandatory. The cut-off frequency is calculated by the following equation [24]:…”

“…The cut-off frequency parameter is calculated after calculating transconductance (g m ) and gate capacitance (C g ) by the following equations, where Q g is the total charge in the channel region [24]:…”

“…The subthreshold swing theoretical limit for MOS-CNTFETs is 60 mV/dec at room temperature, but T-CNTFETs have much better subthreshold swing than the MOS-like structure; therefore, these devices are proper candidates for applications with very low power consumption [2][3][4][5][6][7][8][9]26]. Despite desirable characteristics such as low power consumption, T-CNTFETs suffer from drawbacks such as small current ratio [9,24]. To benefit from the advantages of T-CNTFETs and improve their drawbacks, in this paper, a new T-CNTFET whose drain region contains two parts with different impurity distributions is proposed.…”

“…Ambipolar behavior and BTBT which occur at gate reverse voltages (i.e., at high leakage current) are among the important issues for MOS-CNTFETs [12,14], and should be well addressed in simulations. Some researchers examined these issues and suggested several methods [11,12,[15][16][17][18][19][20][21][22][23][24]. These methods include the change in impurity concentration [11,[15][16][17], bandgap engineering [12], use of linearly and lightly doped impurity injection in source and drain regions [11], underlap engineering [18,20], and use of gate insulators with asymmetrical thicknesses [19], and so on.…”

“…These methods include the change in impurity concentration [11,[15][16][17], bandgap engineering [12], use of linearly and lightly doped impurity injection in source and drain regions [11], underlap engineering [18,20], and use of gate insulators with asymmetrical thicknesses [19], and so on. To improve power consumption and save energy, the T-CNTFETs were proposed [14,24,25]. The subthreshold swing theoretical limit for MOS-CNTFETs is 60 mV/dec at room temperature, but T-CNTFETs have much better subthreshold swing than the MOS-like structure; therefore, these devices are proper candidates for applications with very low power consumption [2][3][4][5][6][7][8][9]26].…”