Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates

Kükner, Halil; Khan, Shahzad; Weckx, Pieter; Raghavan, Praveen; Hamdioui, Said; Kaczer, B.; Catthoor, Francky; Perre, Liesbet Van der; Lauwereins, Rudy; Groeseneken, G.

doi:10.1109/tdmr.2013.2267274

Cited by 49 publications

(15 citation statements)

References 29 publications

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“…By inspecting the atomistic BTI-related literature, it is evident that it lacks a comprehensive atomistic BTI modeling flow for subsystem-wide reliability analysis. Previous works have been mostly focusing either on simple CMOS logic gates [3,13] and SRAM cells [5,10,11,14] or on larger netlists of repetitive logic subblocks with reduced functional complexity [4,15,16]. Thus, we observe a limited usability of SotA atomistic BTI models for more complex netlists and realistic CPU modules.…”

Section: Related Work and Motivationmentioning

confidence: 93%

“…Minority carriers are trapped and emitted from these sites, leading to V th fluctuations. A variety of related imple- [3,13] CMOS Logic Gates 6 Gates [10,14] 6T SRAM cell 6 Gates [5,11] subset of SRAM 244 Gates [15] Benchmark Circuits 68,000 RTL/ALU [4] Array Multiplier 229,376 RTL/ALU [16] Logic Subblocks * N/A * * RTL/ALU Ours CPU module 1830 Subsystem * Adders, multipliers, mux-demux and shifter blocks * * Not explicitly reported mentations exist, modeling BTI either over arbitrary circuit lifetime intervals [10] or in a transient way [11]. However, atomistic BTI modeling comes with increased processing overheads.…”

Section: Related Work and Motivationmentioning

confidence: 99%

See 1 more Smart Citation

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models

Stamoulis

Rodopoulos²,

Meyer

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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In this paper, we propose EDA methodologies for efficient, datapath-wide reliability analysis under Bias Temperature Instability (BTI). The proposed EDA flow combines the efficiency of atomistic, pseudo-transient BTI modeling with the accuracy of commercial Static Timing Analysis (STA) tools. In order to reduce the transistor inventory that needs to be tracked by the STA solver, we develop a thresholdpruning methodology to identify the variation-critical part of a design. That way, we accelerate variation-aware STA iterations, with a maximum speedup of 6.82x achieved for representative benchmark circuits. We substantiate the efficiency of the proposed framework for realistic designs. For a CPU datapath, our threshold-pruning technique outperforms built-in pruning commands of the STA solver by 16.87% in terms of runtime improvement. We demonstrate the impact of BTI after three years of operation, with clock frequency degradation up to 24% and functional yield reduction below 90% for higher frequencies.

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Section: Related Work and Motivationmentioning

confidence: 93%

Section: Related Work and Motivationmentioning

confidence: 99%

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models

Stamoulis

Rodopoulos²,

Meyer

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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show abstract

“…A large body of previous works has focused on either simple CMOS logic gates [2,8], SRAMs [4,14,15], or larger netlists of repetitive blocks with reduced functional complexity [5,7]. Rodopoulos et al have implemented atomistic models on top of transient SPICE simulators [3,5].…”

Section: Related Work and Motivationmentioning

confidence: 99%

“…However, monitoring the activity of several defects per transistor throughout the design lifetime poses severe restrictions on the circuit size, the amount of time samples (and hence the granularity of the workload stimuli), and simulation time. Consequently, existing works limit their exploration to simple gates [2,8], SRAM cells [14,15], and simple logic blocks [5,9].…”

Section: Introductionmentioning

confidence: 99%

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components

Stamoulis

Corbetta

Rodopoulos

et al. 2016

Proceedings of the 26th Edition on Great Lakes Symposium on VLSI

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Atomistic-based approaches accurately model Bias Temperature Instability phenomena, but they suffer from prolonged execution times, preventing their seamless integration in system-level analysis flows. In this paper we present a comprehensive flow that combines the accuracy of Capture Emission Time (CET) maps with the efficiency of the Compact Digital Waveform (CDW) representation. That way, we capture the true workload-dependent BTI-induced degradation of selected CPU components. First, we show that existing works that assume constant stress patterns fail to account for workload dependency leading to fundamental estimation errors. Second, we evaluate the impact of different real workloads on selected CPU sub-blocks from a commercial processor design. To the best of our knowledge, this is the first work that combines atomistic property and true workload-dependency for variability analysis.

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“…Defects increase the threshold voltage (V th ), degrade device performance, and cause bias temperature instability (BTI). [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19] We evaluate the relationship between PID and oscillation frequency. We fabricate a chip including ring oscillators with an antenna structure on a single stage and measure the initial and long-term frequencies of the ring oscillators.…”

Section: Introductionmentioning

confidence: 99%

Initial and long-term frequency degradation of ring oscillators caused by plasma-induced damage in 65 nm bulk and fully depleted silicon-on-insulator processes

Kishida¹,

Oshima

Yabuuchi

et al. 2015

Jpn. J. Appl. Phys.

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The degradation of reliability caused by plasma-induced damage (PID) has become a significant concern with the miniaturization of device size. In particular, it is difficult to relieve PID in silicon-on-insulator (SOI) because it contains buried oxide (BOX) layers. In this work, we compare PID between a bulk and a silicon on thin BOX (SOTB), which has BOX layers of less than 10 nm. We measure frequencies of ring oscillators with an antenna structure on a single stage. In the bulk, PID is relieved by first connecting an antenna to a drain because electric charge flows to a substrate. The difference in initial frequency is 0.79% between structures, which cause and relieve PID. SOTB also relieves the same amount of PID. Initial frequencies are affected by PID, but there is no effect of PID on the long-term degradation mainly caused by bias temperature instability (BTI).

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Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates

Cited by 49 publications

References 29 publications

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components

Initial and long-term frequency degradation of ring oscillators caused by plasma-induced damage in 65 nm bulk and fully depleted silicon-on-insulator processes

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