Comparison of slicing-induced damage in hexagonal SiC by wire sawing with loose abrasive, wire sawing with fixed abrasive, and electric discharge machining

Ishikawa, Yukari; Yao, Yongzhao; Sugawara, Yoshihiro; Sato, Kōji; Okamoto, Yoshihiro; Hayashi, Noritaka; Dierre, Benjamin; Watanabe, Kentaro; Sekiguchi, Takashi

doi:10.7567/jjap.53.071301

Cited by 20 publications

(5 citation statements)

References 37 publications

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“…399,400) It is also essential to remove the subsurface damage introduced during a polishing process by either chemical-mechanical polishing or appropriate H 2 etching, 401) since the mechanical stress induced by surface polishing can create BPD half loops near the surface. [402][403][404] If such BPD half loops remain at the time of epitaxial growth, the BPD (and TED) density in the epitaxial layer will increase. Using the latest growth technology, the BPD-TED conversion ratio exceeds 99.98% and the BPD density in SiC epitaxial layers is about 0.01-0.2 cm −2 .…”

Section: Threshold Condition For 1ssf Expansionmentioning

confidence: 99%

Defect engineering in SiC technology for high-voltage power devices

Kimoto

Watanabe

2020

Appl. Phys. Express

204

100

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Major features of silicon carbide (SiC) power devices include high blocking voltage, low on-state loss, and fast switching, compared with those of the Si counterparts. Through recent progress in the material and device technologies of SiC, production of 600–3300 V class SiC unipolar devices such as power metal-oxide-semiconductor field-effect transistors (MOSFETs) and Schottky barrier diodes has started, and the adoption of SiC devices has been demonstrated to greatly reduce power loss in real systems. However, the interface defects and bulk defects in SiC power MOSFETs severely limit the device performance and reliability. In this review, the advantages and present status of SiC devices are introduced and then defect engineering in SiC power devices is presented. In particular, two critical issues, namely defects near the oxide/SiC interface and the expansion of single Shockley-type stacking faults, are discussed. The current physical understanding as well as attempts to reduce these defects and to minimize defect-associated problems are reviewed.

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Section: Threshold Condition For 1ssf Expansionmentioning

confidence: 99%

Defect engineering in SiC technology for high-voltage power devices

Kimoto

Watanabe

2020

Appl. Phys. Express

204

100

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“…Ishikawa et al reported that basalplane dislocation loops and stacking faults are introduced in the subsurface by the slicing process, and also that some such defects may remain after the buffing process. 29) Figures 3(a) and 3(b) show CDIC images before and after the CMP process. No significant defects or scratches are detected on the wafer surface.…”

Section: Resultsmentioning

confidence: 99%

Synchrotron X-ray topography analysis of local damage occurring during polishing of 4H-SiC wafers

Sasaki¹,

Matsuhata

Tamura³

et al. 2015

Jpn. J. Appl. Phys.

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Surface defects with a scratch-like appearance are often observed locally on 4H-SiC wafers after epitaxial film (epi-film) growth. Since optical microscopy has only revealed a very flat surface after chemo-mechanical polishing (CMP) and before epi-film growth, the origins of these scratchlike surface defects have remained unknown. Therefore, we investigated the generation mechanism of such surface defects by synchrotron Berg-Barrett X-ray topography. Although only highly flat surfaces are observed by optical microscopy, we found that damaged regions comprising lattice defects are often introduced locally during polishing in the subsurface region. These lattice defects are almost completely removed by hydrogen etching, a pre-process for epi-film growth; however, surface defects associated with step bunching are formed in such damaged areas of the wafer surface. It is clear that local surface defects develop into surface defects with a scratch-like appearance during epi-film growth.

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“…Surface and subsurface damage has been widely investigated in the machining of SiC materials, as it is directly related to the surface integrity, particularly for EDM. Melting and evaporating the workpiece material allows EDM to be employed for drilling [12], milling [13,14], cutting [15], and slicing [16] of SiC irrespective of its hardness.…”

Section: Introductionmentioning

confidence: 99%

“…Thermal energy was suggested to be a main material removal mechanisms in EDM of SiC, and it causes surface damages such as cracks, pores, and rectangular pits [15]. EDM predominantly decomposed SiC and formed Si, C, and cracks [16]. An extra layer over the top of the original surface and a porous layer with plenty of voids underneath was formed through EDM of RB-SiC [10].…”

Section: Introductionmentioning

confidence: 99%

Surface and subsurface damage of reaction-bonded silicon carbide induced by electrical discharge diamond grinding

Rao

Zhang

et al. 2020

International Journal of Machine Tools and Manufacture

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Reaction-bonded silicon carbide (RB-SiC) ceramic, one of the best candidates for large optical mirrors, is difficult to machine because of its high hardness and brittleness. A hybrid process called electrical discharge diamond grinding (EDDG) exhibits potential for improving the machinability of RB-SiC by combining electrical discharge machining (EDM) and diamond grinding. However, this hybrid process leads to damages that differ from those in conventional processes owing to the simultaneous actions of EDM and diamond grinding. In the present study, surface and subsurface damages induced by the interactions between EDM and diamond grinding during the EDDG of RB-SiC were examined. The effect of the discharge energy was considered.The surface and subsurface topographies and microstructures were characterized via scanning electron microscopy, Raman spectroscopy, and transmission electron microscopy. The EDM and grinding zones exhibited distinctive surface topographies and different dominant material removal mechanisms. An increase in the discharge energy facilitated ductile removal of the material and decomposition of SiC. Thus, a thinner subsurface damage layer was obtained compared with that in the less-thermally affected zone. The decomposed C and material migration tended to increase with the discharge energy. Owing to the interactions between EDM and diamond grinding, the subsurface was a mixture of amorphous/crystalline C, polycrystalline/nanocrystalline

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Comparison of slicing-induced damage in hexagonal SiC by wire sawing with loose abrasive, wire sawing with fixed abrasive, and electric discharge machining

Cited by 20 publications

References 37 publications

Defect engineering in SiC technology for high-voltage power devices

Defect engineering in SiC technology for high-voltage power devices

Synchrotron X-ray topography analysis of local damage occurring during polishing of 4H-SiC wafers

Surface and subsurface damage of reaction-bonded silicon carbide induced by electrical discharge diamond grinding

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