Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor

Abstract

POWER6 TM is a dual-core microprocessor fabricated in a 65nm SOI process with 10 levels of low-dielectric copper interconnects. The die, shown in Fig. 16.7.1, measures 341mm 2 , contains over 700M transistors, delivers clock frequencies exceeding 5GHz in high-performance applications, and consumes less than 100W in power-sensitive applications [1]. Chips with split and connected core power supplies are fabricated, modeled, and tested, showing both the advantages and disadvantages of each, with important implications for chips with large numbers of cores. One of the power grid designs has the two processor cores on isolated logic power boundaries. The other design has both cores tied into the rest of the chip (called the nest) on both the chip and package.There are advantages and disadvantages for each of the two power grid designs. The split cores allow for independent voltagetuning optimizing power versus performance. The manufactured die has systematic and non-systematic variation across the chip that can make one core faster and have higher leakage than the other, but both cores run at the same clock frequency on POWER6. With separate power domains, the voltage can be lowered on the core with faster circuits. This is done on previous generations of PowerPC microprocessors [2]. Another advantage of split cores is supporting power down modes for an unused core. The disadvantage of the split power grid is that the cores do not benefit from being connected with the relatively quiet nest. The cores consume considerably more power and have much higher dI/dt than the nest, which is made up of mostly level-2 cache and I/O. With cores and nest connected, the cores get the benefit of sharing the quiet on-chip nest capacitance and also share a lower-inductance path to the package decoupling capacitors, further reducing power noise in the cores. Figure 16.7.2 is a simple schematic illustrating the mid-frequency characteristics of the chip and package power distribution. In the figure, R1, C1, L1, and R2 represent the package, which, for the POWER6 package, has a 125MHz resonant frequency. C2 is the intrinsic wire and device capacitance. R3 and C3 represent the added on-chip decoupling capacitance. R4 represents the (nonlinear) leakage and R5 is used to cause the current step in simulation. A single POWER6 core is capable of causing a 13W power step within about 20 clock cycles. Detailed chip-package simulation predicts this causes a 130mV power droop when the cores are split. When the cores are tied, this droop is cut in half.

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

“…Today's production processors use operating voltage margins that are nearly 20% of nominal supply voltage [1], but ‡ This work was done while V. J. Reddi was a student at Harvard. trends indicate that margins will need to grow in order to accommodate worsening peak-to-peak voltage swings.…”

“…1 shows the worst-case peak-to-peak swing in future generations relative to today's 45nm process technology. 1 Voltage swing doubles by the 16nm technology node. Fig.…”

Extreme-scale computer architecture: Energy efficiency from the ground up

“…In addition, small V dd domains are more susceptible to variations in the load offered to the power grid, due to lacking as much averaging effects as a whole-chip V dd domain. These variations in the load induce V dd droops that need to protected against with larger V dd guardbands [9] -also hardly acceptable in an efficiency-first environment. Finally, conventional SVRs take a lot of area and, therefore, including several of them on chip is unappealing.…”

Performance boosting under reliability and power constraints

“…The guardbands protect against process variations, system power supply variations, and workload-induced voltage droops. These margins are set conservatively, and are on the order of 15% to 20% of the supply voltage [6]. However, standard applications running under normal conditions do not exhibit voltage variations anywhere close to the worst-case margins [10].…”