Comparison of the FPGA Implementation of Two Multilevel Space Vector PWM Algorithms

López, Oscar L.; Alvarez, J.; Doval-Gandoy, Jesús; Freijedo, Francisco D.; Nogueiras, A.; Lago, A.; Penalver, C.M.

doi:10.1109/tie.2008.917159

Cited by 122 publications

(63 citation statements)

References 42 publications

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“…Although the FPGA allow a high degree of parallelism in the implementation of PWM algorithms, it is necessary to reduce the total quantity of material needed, keeping the final cost to a reasonable point [5]. Most of the polarization circuits and embedded digital (MOS transistors, resistors, NE555, Arduino, etc.)…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Pulse Width Modulation Using Hardware/Software MicroBlaze Soft-Core

Zemmouri¹,

Elgouri²,

Alareqi³

et al. 2017

IJPEDS

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This paper presents an embedded control application of clock frequency to control the pulse width of the output signals, implemented on field programmable get array. This control allows the creation of lines of Pulsewidth modulation depending on the numbers of card outputs, without using the specific "Timers /Counters" blocks; this method is effective to adjust the amount of power supplied to an electrical charge. The purpose of this work is to achieve a real time hardware implementation with higher performance in both size and speed. Performance of these designimplemented in field programmable get array virtex 5 card, and signals displayed on an asciloscope. Keyword:EDK/SDK FPGA Vertix5 Micoblaze PWM

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Section: Introductionmentioning

confidence: 99%

Design and Implementation of Pulse Width Modulation Using Hardware/Software MicroBlaze Soft-Core

Zemmouri¹,

Elgouri²,

Alareqi³

et al. 2017

IJPEDS

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“…As the number of voltage sources increased, the quality of output voltage is much improved. However, a larger number of levels increase the number of devices that must be controlled and the control complexity [9].…”

Section: Introductionmentioning

confidence: 99%

Non-Conventional Multi-level Inverter with Reduced Number of Voltage Sources and Switches

Renuka¹,

Kishor²

2015

International Journal of Innovative Research in Electrical, Ele

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Multilevel inverters have got high quality output when compared with two-level inverters so for high power purposes the usage of Multi-level inverter applications has grow more ubiquitous in industries. In this paper, foremost a new topology for sub-multi level inverters is proposed and then the series connection of sub-multilevel inverters is put forth as a generalized multilevel inverter. This proposed multi level inverter has reduced number of switching devices. The optimal structure concerning the criteria such as standard voltage on the switches, number of switches and number of dc voltage sources etc is succeed by paying a special attention. Asymmetric condition is verified for proposed multilevel inverter by using MATLAB SIMULINK software.

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“…In recent year, several modulation strategies for a threelevel NPC VSI have been developed [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30]. They could be mainly classified into carrier-based pulsewidth modulation (CB-PWM) [11][12][13][14][15][16][17][18], space vector modulation (SVM) [19][20][21][22][23][24][25][26], and selective harmonic elimination (SHE) [27][28][29][30].…”

Section: Introductionmentioning

confidence: 99%

“…They could be mainly classified into carrier-based pulsewidth modulation (CB-PWM) [11][12][13][14][15][16][17][18], space vector modulation (SVM) [19][20][21][22][23][24][25][26], and selective harmonic elimination (SHE) [27][28][29][30]. Among these PWM strategies, the CB-PWM has probably been the most popular due to its simplicity of implementation, which based on the comparison between the modulation reference signals and two triangular carriers.…”

Section: Introductionmentioning

confidence: 99%

Modified Unipolar Carrier-Based PWM Strategy for Three-Level Neutral-Point-Clamped Voltage Source Inverters

Srirattanawichaikul¹,

Premrudeepreechacharn²,

Kumsuwan³

2014

Journal of Electrical Engineering and Technology

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-This paper presents a simple modified unipolar carrier-based pulsewidth modulation (CB-PWM) strategy for the three-level neutral-point-clamped (NPC) voltage source inverter (VSI). Analytical expressions for the relationship between modulation reference signals and output voltages are derived. The proposed modulation technique for the three-level NPC VSI includes the maximum and minimum of the three-phase sinusoidal reference voltages with zero-sequence voltage injection concept. The proposed modified CB-PWM strategy incorporates a novel method that requires only of one triangular carrier wave for generate the gating pulses in three-level NPC VSI. It has the advantages of being simplifying the algorithm with no need of complex two/multi-carrier pulsewidth modulation or space vector modulation (SVM) and it's also simple to implement. The possibility of the proposed CB-PWM technique has been verified though computer simulation and experimental results.

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Comparison of the FPGA Implementation of Two Multilevel Space Vector PWM Algorithms

Cited by 122 publications

References 42 publications

Design and Implementation of Pulse Width Modulation Using Hardware/Software MicroBlaze Soft-Core

Design and Implementation of Pulse Width Modulation Using Hardware/Software MicroBlaze Soft-Core

Non-Conventional Multi-level Inverter with Reduced Number of Voltage Sources and Switches

Modified Unipolar Carrier-Based PWM Strategy for Three-Level Neutral-Point-Clamped Voltage Source Inverters

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