In the last few years, interest in multiphase converter technology has increased due to the benefits of using more than three phases in drive applications. Besides, multilevel converter technology permits the achievement of high power ratings with voltage limited devices. Multilevel multiphase technology combines the benefits of both technologies, but new modulation techniques must be developed in order to take advantage of multilevel multiphase converters. In this paper, a novel space vector pulsewidth modulation (SVPWM) algorithm for multilevel multiphase voltage source converters is presented. This algorithm is the result of the two main contributions of this paper: the demonstration that a multilevel multiphase modulator can be realized from a two-level multiphase modulator, and the development of a new two-level multiphase SVPWM algorithm. The multiphase SVPWM algorithm presented in this paper can be applied to most multilevel topologies; it has low computational complexity and it is suitable for hardware implementations. Finally, the algorithm was implemented in a low-cost field-programmable gate array and it was tested in a laboratory with a real prototype using a five-level five-phase inverter.Index Terms-Field-programmable gate array (FPGA), modulation algorithm, multilevel multiphase converter, space vector pulsewidth modulation (SVPWM).

No abstract

Multilevel multiphase technology combines the benefits of multilevel converters and multiphase machines. Nevertheless, new modulation techniques must be developed to take advantage of multilevel multiphase converters. In this paper, a new space vector pulsewidth modulation algorithm for multilevel multiphase voltage source converters with switching state redundancy is introduced. As in three-phase converters, the switching state redundancy permits to achieve different goals like extending the modulation index and reducing the number of switchings. This new algorithm can be applied to the most usual multilevel topologies; it has low computational complexity, and it is suitable for hardware implementations. Finally, the algorithm was implemented in a field-programmable gate array, and it was tested by using a five-level five-phase inverter feeding a motor.Index Terms-Field-programmable gate array (FPGA), multilevel converter, multiphase machine, space vector pulsewidth modulation (SVPWM), switching state redundancy.

No abstract

No abstract