Comparison of the Hot Carrier Degradation of N- and P-Type Fin Field-Effect Transistors in 14-nm Technology Nodes

Band‐to‐Band Tunneling Control by External Forces: A Key Principle and Applications

“…Several studies have tried to implement ternary inverters using tunneling devices, which exhibit NDR characteristics. [ 11,22,101 ] In 2020, Choi et al. fabricated the type‐III junction 2D p‐MoTe 2 /organic n‐HAT‐CN and 2D p‐WSe 2 /n‐MoO x hybrid heterostructure instead of a conventional 2D–2D heterojunction, which is difficult to form a type‐III junction.…”

“…For this reason, a lot of effort has been put into applying the tunneling phenomenon to the photodetector applications. [ 22,118 ] In 2021, Woo et al. enhanced the photodoping‐based BTBT of the IGZO/p‐Si photodetector via a self‐assembled monolayer (SAM) doping and annealing process, demonstrating a 100‐fold improvement in the on/off current ratio ( Figure a).…”

“…[ 5 ] The scaling down of MOSFET has been challenging as the power management of IC strongly influences the production price and reliability. Currently, various breakthroughs have been suggested to resolve the limitation in scaling down conventional MOSFETs, such as increasing the data density in a unit area (such as multilevel logic, [ 6–11 ] memory computing, [ 12–15 ] and other area‐efficient method [ 16–18 ] ) and improving in device architecture (such as FinFET, [ 19–22 ] gate‐all‐around (GAA) FET, [ 22–28 ] tunneling field‐effect transistor (TFET) [ 22,29–31 ] ).…”

“…For this reason, the BTBT‐based TFET can realize a steep subthreshold swing of less than 60 mV dec ‐1 . [ 22,34,35 ] Moreover, the dominant mechanism of charge transport from the tunneling current to the thermionic current during voltage sweeping, folded current–voltage characteristic, called negative differential resistance (NDR), is generated, which exhibits multiple threshold voltages. [ 36–40 ] Their notable characteristics have been exploited to implement multi‐valued logic applications, which are key elements for high‐information‐density digital electronics.…”

Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs

“…In contrast to SCEs, improving device reliability during device minimization has become increasingly difficult. For example, recently, gate dielectric damage from hotcarrier injection (HCI), which is associated with the lateral drain electric field, has resurfaced as a matter of concern in semiconductor devices [2,3]. Typically, HCI increases both the threshold voltage (V T ) and SS, and hence results in unwanted V T mismatching while also increasing I OFF in circuitries.…”