Compendium of Single Event Transient (SET) and Total Ionizing Dose (TID) Test Results for Commonly Used Voltage Comparators

Bozovich, Amanda N.; Irom, F.

doi:10.1109/nsrec.2017.8115430

Cited by 4 publications

(5 citation statements)

References 53 publications

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“…200 mV in [29,30] and 100 mV in [31]) to several mV (e.g. 1 mV in [32] and 15 mV in [33]) depending on circuits' application, which helps to increase the SET vulnerability in analog systems. As mentioned before, in this work we adopt threshold of ±50 mV, which is about '10% of full-scale' and is prevalently adopted in the reliability community to filter out ASETs by amplitude.…”

Section: Discussionmentioning

confidence: 99%

Pulse quenching based radiation-hardened by design technique for analog single-event transient mitigation on an operational amplifier in 28 nm bulk CMOS process

Liu

Sun

et al. 2020

Semicond. Sci. Technol.

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In nanometer bulk CMOS processes, multi-node charge collection induced by a heavy-ion strike is prevalent. Pulse quenching caused by charge sharing between the struck node (termed as active device) and the following gate (termed as passive device) has been widely studied in digital circuits. This paper firstly demonstrates that the pulse quenching effect also exists between the adjacent stages of analog circuits and can be used to mitigate analog single-event transient (ASET) perturbation. Contrary to digital circuits, whose propagated SET is minimized with the charge collected by passive device maximized, simulation results indicate that there is an optimal spacing between the active and passive devices in analog circuits. When the spacing is too close, the SET induced by the hit node is efficiently mitigated by pulse quenching effect, but the disturbance caused by the charge sharing collection in passive device becomes dominant. Simulation results show that pulse quenching effect has a dual role in ASET mitigation. This paper provides innovative guidance to the radiation-hardening design for analog circuits.

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Section: Discussionmentioning

confidence: 99%

Pulse quenching based radiation-hardened by design technique for analog single-event transient mitigation on an operational amplifier in 28 nm bulk CMOS process

Liu

Sun

et al. 2020

Semicond. Sci. Technol.

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show abstract

“…Typical hardening methods are to increase the fault tolerance of the circuit, introduce a larger RC constant by directly increasing the capacitance value or adding the decoupling resistance, 20 and improve the critical charge by adjusting the device size. [21][22][23][24] These methods will cause great losses in speed, power, and area, and the hardening performance is limited. In addition, special processes developed for single-event latch-up (SEL) and enhanced low dose rate sensitivity (ELDRS) effect have also been reported.…”

Section: Previous Hardening Techniquesmentioning

confidence: 99%

“…In addition, special processes developed for single-event latch-up (SEL) and enhanced low dose rate sensitivity (ELDRS) effect have also been reported. 21,22 Triple modular redundant (TMR) is a common hardening technique. [21][22][23][24] The IS9-139ASRH hardened quad comparator developed based on Intersil's RSG process 21,22 makes redundancy for every comparator and current reference, so that each redundant comparator within each channel has a different current reference bias, which brings higher operating voltage, power consumption, and a larger area.…”

Section: Previous Hardening Techniquesmentioning

confidence: 99%

“…21,22 Triple modular redundant (TMR) is a common hardening technique. [21][22][23][24] The IS9-139ASRH hardened quad comparator developed based on Intersil's RSG process 21,22 makes redundancy for every comparator and current reference, so that each redundant comparator within each channel has a different current reference bias, which brings higher operating voltage, power consumption, and a larger area. It also greatly increases the complexity of the chip, bringing challenges to the layout and package.…”

Section: Previous Hardening Techniquesmentioning

confidence: 99%

“…These methods will cause great losses in speed, power, and area, and the hardening performance is limited. In addition, special processes developed for single‐event latch‐up (SEL) and enhanced low dose rate sensitivity (ELDRS) effect have also been reported 21,22 …”

Section: Set Hardening Techniques Of Comparatormentioning

confidence: 99%

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A novel high‐precision single‐event transient hardened voltage comparator design

Xie

Liu

et al. 2023

Circuit Theory & Apps

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SummaryTo reduce the impact of the single‐event transient (SET) effect on the high‐precision comparator, based on the common high‐gain pre‐amplification stage structure of the comparator, a new radiation hardened by design (RHBD) method, namely, the sensitive node transient detection feedback latch (SNTDFL) technique, is proposed. The hardening technique avoids comparator erroneous output by detecting the sensitive nodes of the high‐gain pre‐amplification stage. The detection circuit receives the response generated by the high energy particle impacts and feeds the high level back to the sensitive nodes to latch the current comparator state. In this paper, a novel high‐precision SET hardened voltage comparator based on this technique is developed. Through detailed circuit principle and simulation analysis, the functional characteristics and the hardening performance of the high‐precision hardened comparator are verified. Compared with the unhardened and the TMR technique hardened comparator, the SNTDFL technique hardened comparator effectively avoids the erroneous output caused by the SET effect with less overhead and still has excellent functional characteristics.

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Total dose effects on large quantities of LM239N comparators from two manufacturers

Sharp¹,

Voegtli²,

Bradley

2021

2021 21th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

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Compendium of Single Event Transient (SET) and Total Ionizing Dose (TID) Test Results for Commonly Used Voltage Comparators

Cited by 4 publications

References 53 publications

Pulse quenching based radiation-hardened by design technique for analog single-event transient mitigation on an operational amplifier in 28 nm bulk CMOS process

Pulse quenching based radiation-hardened by design technique for analog single-event transient mitigation on an operational amplifier in 28 nm bulk CMOS process

A novel high‐precision single‐event transient hardened voltage comparator design

Total dose effects on large quantities of LM239N comparators from two manufacturers

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