Compensation and Calibration Techniques for Current-Steering DACs

McDonnell, Samantha; Patel, Vaama; Duncan, Lucas; Dupaix, Brian; Khalil, Waleed

doi:10.1109/mcas.2017.2689518

Cited by 33 publications

(14 citation statements)

References 53 publications

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“…The suppression of the image replica degrades to −16 dB, for example, if the alignment between the two clocks is ±18 • away from the desired phase difference of 180 • ; and the image can be reduced by more than −56 dB for smaller than 0.1% timing errors. Although a 0.1% timing error is a hard requirement at GHz clock speeds, this is in line with current developments [20]. For example, calibration down to 0.013% timing error at a clock rate of 2GS/s has been demonstrated in 130nm BiCMOS technology [8].…”

Section: B Iq Imbalancesupporting

confidence: 67%

All-Digital Transmitter Architecture Based on Two-Path Parallel 1-bit High Pass Filtering DACs

Gebreyohannes

Frappé

Cathelin

et al. 2018

IEEE Trans. Circuits Syst. I

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This paper presents a novel transmitter architecture which is tailored for low power, all-digital, and high speed implementation. It is based on two-path parallel digital-to-analog converters (DAC) which are driven by 180 • phase-shifted clocks. The architecture operates in high pass mode and extends the output carrier frequency up to half the DAC clock rate. To decrease the number of analog unit current cells in the converter, a lowpass-modulator is used. Since the modulator also converts the input resolution to 1-bit, an inherently-linear digital-toanalog conversion is realized by embedding filtering in the DAC. Furthermore, the finite impulse response DAC transfer function is designed to cancel the-modulator quantization noise. Simulation results at system level demonstrate the robustness of the architecture against random coefficient mismatches, and its suitability for broadband transmissions. The error vector magnitude of the quadrature output is simulated for up to 15% random coefficient mismatch and it maintains a value below −22 dB even when the input signal bandwidths vary from 20 MHz (64-subcarrier OFDM) to 160 MHz (512-subcarrier OFDM). Experimental results are presented to discuss the validity of the proposed all-digital transmitter architecture and to highlight the challenges of implementing it in advanced CMOS nodes. Index Terms-Digital transmitter, high pass FIR DACs, time-interleaving, parallel DACs.

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Section: B Iq Imbalancesupporting

confidence: 67%

All-Digital Transmitter Architecture Based on Two-Path Parallel 1-bit High Pass Filtering DACs

Gebreyohannes

Frappé

Cathelin

et al. 2018

IEEE Trans. Circuits Syst. I

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“…A current-steering DAC can be used in the feedback path. To achieve higher resolutions with good performance it is necessary to segment the feedback DAC (Moody, 2014). In the ADC presented here the DAC is segmented into 3-bit bi- nary encoded registers and 7-bit thermometer encoded registers.…”

Section: Introductionmentioning

confidence: 99%

“…A binary encoding has the advantage of short conversion time, though also has worse monotonicity at higher resolutions. The MSBs are therefore thermometer encoded, which has a better monotonicity and means that less effort is required for error compensation (McDonnell, 2017). A drawback of this type of encoding is a slower transition, though this is less essential for MSBs.…”

Section: Introductionmentioning

confidence: 99%

“…A drawback of this type of encoding is a slower transition, though this is less essential for MSBs. The main disadvantage, however, is that a binary to thermometer decoder is needed, which would increase the power consumption (Radulov, 2006;Nazari, 2016). In order to avoid having to use this decoder a control with an up/down signal is implemented.…”

Section: Introductionmentioning

confidence: 99%

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10-bit tracking ADC with a multi-bit quantizer, variable step size and segmented current-steering DAC

Bramburger

Killat

2019

Adv. Radio Sci.

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Abstract. This paper presents a 10-bit tracking ADC using a multi-bit quantiser and a segmented current-steering DAC. The quantiser allows a dynamical adjustment of the step size dependent on the input signal waveform. This mitigates the limited slew rate of delta encoded ADCs. Energy consumption induced by 1 LSB ripple is removed by the quantiser. The segmented current-steering DAC allows simple control, good monotonicity and improved transient response when compared to previous design as well as potential power reduction.

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“…Static time errors are time-invariant and are caused by mismatches in clock routing (∆t s1 ), clock-to-Q and propagation delay (∆t s2 , ∆t s3 ), and switching speed (∆t s4 ) [6]. Dynamic time errors vary over each clock period and are caused by deterministic jitter in the data path (∆t d2 , ∆t d3 )as well as data-dependent offset in the switches caused by fluctuations in the common source node (∆t d4 )[6,7].…”

mentioning

confidence: 99%