Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache

Li, Qingan; He, Yanxiang; Li, Jianhua; Shi, Liang; Chen, Yiran; Xue, Chun Jason

doi:10.1109/tc.2014.2360527

Cited by 23 publications

(13 citation statements)

References 22 publications

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“…For the data arrays which are useful during the whole program execution time, a DRAM-style refresh method is employed to refresh them during the whole execution period. For the data arrays whose MWIs' lifetime only lasts for a period of the whole program execution time, a reasonable N-refresh method [33] …”

Section: Methodsmentioning

confidence: 99%

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems

Qiu

et al. 2016

IEEE Trans. Comput.

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Architecting PCM, especially MLC PCM, as main memory for MCUs is a promising technique to replace conventional DRAM deployment. However, PCM/MLC PCM suffers from long write latency and large write energy. Recent work has proposed a compiler directed dual-write (CDDW) scheme to combat the drawbacks of PCM by adopting fast or slow mode for different write operations. For large-scale loops, we observe that write instances' lifetime is very long and can only be written by the expensive slow mode. This paper proposes a write mode aware loop tiling approach to effectively reduce the lifetime of write instances and maximize the number of efficient fast writes in loops. The experimental results show that the proposed approach improves performance by 50.8% and reduces dynamic energy by 32.0% across a set of benchmarks compared to the CDDW approach on average. research interests include memory and parallelism optimization for embedded systems, software/hardware co-design, real time systems and computer security.

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Section: Methodsmentioning

confidence: 99%

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems

Qiu

et al. 2016

IEEE Trans. Comput.

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“…For the data arrays which are useful during the whole program execution time, a DRAM-style refresh method is employed. For the data arrays whose MWIs' lifetime only lasts for a portion of the whole program execution time, a reasonable N-refresh method [11] is employed, where the data arrays are refreshed 2 N − 1 times of the fast write retention time. The N-refresh method prolongs the fast MWIs' validation time.…”

Section: Methodsmentioning

confidence: 99%

Write mode aware loop tiling for high performance low power volatile PCM

Qiu

2014

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

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Architecting PCM, especially MLC PCM, as main memory for MCUs is a promising technique to replace conventional DRAM deployment. However, PCM/MLC PCM suffers from long write latency and large write energy. Recent work has proposed a compiler directed dual-write (CDDW) scheme to combat the drawbacks of PCM by adopting fast or slow write mode for different write operations. We observe that write instances' lifetime is very long and can only be written by the expensive slow mode for large-scale loops. This paper proposes a write mode aware loop tiling approach to effectively reduce the lifetime of write instances and maximize the number of efficient fast writes in loops. The experimental results show that the proposed approach improves performance by 50.8% and reduces dynamic energy by 32.0% across a set of benchmarks compared to the CDDW approach on average.

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“…Another approach to alleviate the cost of write operations is to relax its non-volatility property. In [18], authors brought forward the retention time of NVMs. The retention time is the time throughout data is retained stored.…”

Section: B Compiler Optimizations Targeting Nvmmentioning

confidence: 99%

Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs

Péneau

Bouziane

Abdoulayse

et al. 2016

2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Energy-efficiency is one of the most challenging design issues in both embedded and high-performance computing domains. The aim is to reduce as much as possible the energy consumption of considered systems while providing them with the best computing performance. Finding an adequate solution to this problem certainly requires a cross-disciplinary approach capable of addressing the energy/performance trade-off at different system design levels. In this paper, we present an empirical impact analysis of the integration of Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) technologies in multicore architectures when applying some existing compiler optimizations. For that purpose, we use three well-established architecture and NVM evaluation tools: NVSim, gem5 and McPAT. Our results show that the integration of STT-MRAM at cache memory levels enables a significant reduction of the energy consumption (up to 24.2 % and 31 % on the considered multicore and monocore platforms respectively) while preserving the performance improvement provided by typical code optimizations. We also identify how the choice of the clock frequency impacts the relative efficiency of the considered memory technologies.

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Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache

Cited by 23 publications

References 22 publications

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems

Write mode aware loop tiling for high performance low power volatile PCM

Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs

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