Compiling for VLIW DSPs

Keßler, Christoph

doi:10.1007/978-1-4419-6345-1_22

Cited by 3 publications

(3 citation statements)

References 65 publications

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“…They typically are less scalable but can deliver better solutions than isolated approaches. A particular focus has been on VLIW processors, for which the interdependencies between both problems are strong [55]. As Table 2 shows, our integrated approach is the first that matches the practicality of isolated register allocation approaches.…”

Section: Combinatorial Instruction Schedulingmentioning

confidence: 96%

“…Furthermore, for functions where Unison times out, the smallest and largest gaps are achieved for Hexagon and MIPS respectively, independently of function size. The fact that Unison scales better for Hexagon (a VLIW processor) than for ARM and MIPS (single-issue processors) is surprising as the latter are considered easier to handle by heuristic approaches [55]. The fact that Unison scales better for ARM than for MIPS is also unexpected, as ARM includes more features for the solver to deal with such as selection of 16-and 32-bit instructions (see Section 4.3) and double-load and double-store instructions (see Section 9).…”

Section: Scalabilitymentioning

confidence: 99%

See 1 more Smart Citation

Combinatorial Register Allocation and Instruction Scheduling

Lozano

Carlsson

Blindell

et al. 2019

ACM Trans. Program. Lang. Syst.

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This paper introduces a combinatorial optimization approach to register allocation and instruction scheduling, two central compiler problems. Combinatorial optimization has the potential to solve these problems optimally and to exploit processor-specific features readily. Our approach is the first to leverage this potential in practice: it captures the complete set of program transformations used in state-of-the-art compilers, scales to mediumsized functions of up to 1000 instructions, and generates executable code. This level of practicality is reached by using constraint programming, a particularly suitable combinatorial optimization technique. Unison, the implementation of our approach, is open source, used in industry, and integrated with the LLVM toolchain.An extensive evaluation confirms that Unison generates better code than LLVM while scaling to mediumsized functions. The evaluation uses systematically selected benchmarks from MediaBench and SPEC CPU2006 and different processor architectures (Hexagon, ARM, MIPS). Mean estimated speedup ranges from 1.1% to 10% and mean code size reduction ranges from 1.3% to 3.8% for the different architectures. A significant part of this improvement is due to the integrated nature of the approach. Executing the generated code on Hexagon confirms that the estimated speedup results in actual speedup. Given a fixed time limit, Unison solves optimally functions of up to 946 instructions, nearly an order of magnitude larger than previous approaches.The results show that our combinatorial approach can be applied in practice to trade compilation time for code quality beyond the usual compiler optimization levels, identify improvement opportunities in heuristic algorithms, and fully exploit processor-specific features. This paper is partially based on preliminary work presented at the Principles and Practice of Constraint Programming (2012) [20]; Languages, Compilers, and Tools for Embedded Systems (2014) [21]; and Compiler Construction (2016) [22] conferences. Compared to the preliminary work, this paper is completely restructured and rewritten, completes the combinatorial model with rematerialization, proposes extensions to capture additional program transformations and processor-specific features, and contributes a more exhaustive evaluation. Additions to the evaluation include more benchmarks and processors, evidence of the fundamental benefit of the integrated approach, an in-depth study of scalability, and actual execution measurements.

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Section: Combinatorial Instruction Schedulingmentioning

confidence: 96%

Section: Scalabilitymentioning

confidence: 99%

Combinatorial Register Allocation and Instruction Scheduling

Lozano

Carlsson

Blindell

et al. 2019

ACM Trans. Program. Lang. Syst.

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show abstract

“…In addition, Appendices A and B review and classify (Tables 5 and 7) register pressure-aware instruction scheduling and integrated approaches to the three compiler back-end tasks. The paper complements available surveys of register allocation [91,122,128,133,134], instruction scheduling [2,42,68,136,139], and integrated code generation [97], whose focus tends to be on heuristic approaches.…”

Section: Rp-instruction Scheduling Register Allocation Instruction Sc...mentioning

confidence: 99%

Survey on Combinatorial Register Allocation and Instruction Scheduling

Lozano

Schulte

2019

ACM Comput. Surv.

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Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to increase instruction-level parallelism) are essential tasks for generating efficient assembly code in a compiler. In the past three decades, combinatorial optimization has emerged as an alternative to traditional, heuristic algorithms for these two tasks. Combinatorial optimization approaches can deliver optimal solutions according to a model, can precisely capture trade-offs between conflicting decisions, and are more flexible at the expense of increased compilation time. This article provides an exhaustive literature review and a classification of combinatorial optimization approaches to register allocation and instruction scheduling, with a focus on the techniques that are most applied in this context: integer programming, constraint programming, partitioned Boolean quadratic programming, and enumeration. Researchers in compilers and combinatorial optimization can benefit from identifying developments, trends, and challenges in the area; compiler practitioners may discern opportunities and grasp the potential benefit of applying combinatorial optimization.

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