Compiling high throughput network processors

Abstract

Gorilla is a methodology for generating FPGA-based solutions especially well suited for data parallel applications with fine grain irregularity. Irregularity simultaneously destroys performance and increases power consumption on many data parallel processors such as General Purpose Graphical Processor Units (GPGPUs). Gorilla achieves high performance and low power through the use of FPGA-tailored parallelization techniques and application-specific hardwired accelerators, processing engines, and communication mechanisms. Automatic compilation from a stylized C language and templates that define the hardware structure coupled with the intrinsic flexibility of FPGAs provide high performance, low power, and programmability.Gorilla's capabilities are demonstrated through the generation of a family of core-router network processors processing up to 100Gbps (200MPPS for 64B packets) supporting any mix of IPv4, IPv6, and Multi-Protocol Label Switching (MPLS) packets on a single FPGA with off-chip IP lookup tables. A 40Gbps version of that network processor was run with an embedded test rig on a Xilinx Virtex-6 FPGA, verifying for performance and correctness. Its measured power consumption is comparable to full custom, commercial network processors. In addition, it is demonstrated how Gorilla can be used to generate merged virtual routers, saving FPGA resources.

Shire: Making FPGA-accelerated Middlebox Development More Pleasant

“…However, none of these works attempted to provide this at the same time as they provided software flexibility. [5,9,11,13,20]. In this work we demonstrate that it's not only feasible integrate and software flexibility into one development abstraction, but it also demonstrates that there are significant benefits to do doing this.…”

“…FlowBlaze [19] P4 P4VBox [22] P4 ClickNP [11] C (HLS) Gorilla [9] C (HLS) features simultaneously in one FPGA development framework. For instance, the most recent framework HxDP [3], demonstrated a significant number of the development features could be provided by one framework.…”

The Programmable Data Plane

“…High-level synthesis or specialized compilers allow programming FPGAs using languages like C or P4 as opposed to more complex and cumbersome hardware description languages, such as Verilog [200,203]. The balance of high performance together with programmability make FPGAs not only interesting for prototyping but also a powerful alternative to costly and rigid ASIC designs for production environments [16,32,118]. In the context of networking, FPGAs are primarily used on NICs to offload packet processing from servers with the goal of saving precious CPU cycles [60].…”

The Programmable Data Plane: Abstractions, Architectures, Algorithms, and Applications

“…High-level synthesis or specialized compilers allow programming FPGAs using languages like C or P4 as opposed to more complex and cumbersome hardware description languages, such as Verilog [198,201]. The balance of high performance together with programmability make FPGAs not only interesting for prototyping but also a powerful alternative to costly and rigid ASIC designs for production environments [17,33,117]. In the context of networking, FPGAs are primarily used on NICs to offload packet processing from servers with the goal of saving precious CPU cycles [61].…”