Recent proposals have employed optical circuit switching (OCS) to reduce the cost of data center networks. However, the relatively slow switching times (10-100 ms) assumed by these approaches, and the accompanying latencies of their control planes, has limited its use to only the largest data center networks with highly aggregated and constrained workloads. As faster switch technologies become available, designing a control plane capable of supporting them becomes a key challenge.In this paper, we design and implement an OCS prototype capable of switching in 11.5 µs, and we use this prototype to expose a set of challenges that arise when supporting switching at microsecond time scales. In response, we propose a microsecond-latency control plane based on a circuit scheduling approach we call Traffic Matrix Scheduling (TMS) that proactively communicates circuit assignments to communicating entities so that circuit bandwidth can be used efficiently.

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Using a compact (0.03 mm(2)) silicon-photonic bias-free thermo-optic cross-bar switch, we demonstrate microsecond-scale switching of twenty wavelength channels of a C-band wavelength-division multiplexed optical ring network, each carrying 10 Gbit/second data concurrently, with 15 mW electrical power consumption (no temperature control required). A convenient pulsed driving scheme is demonstrated and eye patterns and bit-error rate measurements are shown. An algorithm is developed to measure the power-division ratio between the two output ports, the insertion and switching losses, and non-ideal phase deviations.

We experimentally evaluate the network-level switching time of a functional 23-host prototype hybrid optical circuit-switched/electrical packet-switched network for datacenters called Mordia (Microsecond Optical Research Datacenter Interconnect Architecture). This hybrid network uses a standard electrical packet switch and an optical circuit-switched architecture based on a wavelength-selective switch that has a measured mean port-to-port network reconfiguration time of 11.5 µs including the signal acquisition by the network interface card. Using multiple parallel rings, we show that this architecture can scale to support the large bisection bandwidth required for future datacenters.

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