Compiling SA-C Programs to FPGAs: Performance Results

Draper, Bruce A.; Böhm, A. P. Wim; Hammes, J.; Najjar, Walid; Beveridge, J. Ross; Ross, Charlie; Chawathe, M.; Desai, Mitesh; Bins, José

doi:10.1007/3-540-48222-9_15

Cited by 15 publications

(4 citation statements)

References 2 publications

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“…The intractable nature of the behavioral synthesis problem including the pointer aliasing problem are often resolved by imposing restrictions to the input and front-end resulting in a fragmented landscape of variants [24]- [28]. A customized processor can however support the full ANSI standard and offers additional advantages in modular development through libraries, intuitive single-step debugging, and a fluid design methodology by separately optimizing algorithm, compiler, machine language, and architecture.…”

Section: B Behavioral Synthesismentioning

confidence: 99%

Portable, Flexible, and Scalable Soft Vector Processors

Yiannacouras

Steffan

Rose

2012

IEEE Trans. VLSI Syst.

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Abstract-Field-programmable gate arrays (FPGAs) are increasingly used to implement embedded digital systems, however, the hardware design necessary to do so is time-consuming and tedious. The amount of hardware design can be reduced by employing a microprocessor for less-critical computation in the system. Often this microprocessor is implemented using the FPGA reprogrammable fabric as a soft processor which presently have simple architectures and moderate performance. Our goal is to scale the performance of existing soft processors hence expanding their suitability to more critical computation. To this end we propose extending soft processors with vector extensions to exploit the abundant data parallelism found in many embedded kernels. Such a soft vector processor can execute these kernels much faster than a single-core hence reducing the need for hardware implementations. We observe this improved execution speed through experimentation with vector extended soft processor architecture (VESPA) which is designed, implemented, and evaluated on real FPGA hardware. VESPA is shown to effectively scale performance up to 32 lanes, while providing substantial architectural flexibility to create a fine-grained design space. With these characteristics, and portability across FPGA devices, soft vector processors can provide exact-fit architectures which can efficiently and more easily implement data parallel workloads over custom FPGA hardware design.Index Terms-Customization, design space exploration, field-programmable gate array (FPGA)-based soft-core processors, processor generator.

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Section: B Behavioral Synthesismentioning

confidence: 99%

Portable, Flexible, and Scalable Soft Vector Processors

Yiannacouras

Steffan

Rose

2012

IEEE Trans. VLSI Syst.

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“…One solution is to extend the C language with macro support so that the programmer can define the bit-widths of integer variables as done in Cronquist et al [1998], Draper et al [2001], Frigo et al [2001], and SystemC [2003]. However, this places a significant burden on the programmer to perform extensive analysis in order to specify the actual data bit-widths of each and every variable without a single occurrence of over-or underflow during program execution.…”

Section: Introductionmentioning

confidence: 99%

A stochastic bitwidth estimation technique for compact and low-power custom processors

Özer

Nisbet

Gregg

2008

ACM Trans. Embed. Comput. Syst.

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There is an increasing trend toward compiling from C to custom hardware for designing embedded systems in which the area and power consumption of application-specific functional units, registers, and memory blocks are heavily dependent on the bit-widths of integer operands used in computations. The actual bit-width required to store the values assigned to an integer variable during the execution of a program will not, in general, match the built-in C data types. Thus, precious area is wasted if the built-in data type sizes are used to declare the size of integer operands. In this paper, we introduce stochastic bit-width estimation that follows a simulation-based probabilistic approach to estimate the bit-widths of integer variables using extreme value theory. The estimation technique is also empirically compared to two compile-time integer bit-width analysis techniques. Our experimental results show that the stochastic bit-width estimation technique dramatically reduces integer bit-widths and, therefore, enables more compact and power-efficient custom hardware designs than the compile-time integer bit-width analysis techniques. Up to 37% reduction in custom hardware area and 30% reduction in logic power consumption using stochastic bit-width estimation can be attained over ten integer applications implemented on an FPGA chip.

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“…FPGA compilers like the SA-C compiler [2], mainly performed parallelizing code transformations to utilize the huge arrays of CLBs. Baradaran et al [3] presents a technique to utilize the embedded RAMs as caches, to enable data-reuse.…”

Section: Introductionmentioning

confidence: 99%

A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures

Pal¹,

Balakrishnan

2007

2007 International Conference on Field Programmable Logic and Applications

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This paper presents an approach for efficiently mapping loops and array intensive applications onto FPGA architectures with distributed RAMs, multipliers and logic. We perform a data dependency based, two level partitioning of the application's iteration space under target FPGA architectural constraints, to achieve better performance. It is shown that, this approach can result in a super-linear speedup; linear speedup due to concurrent computation on multiple compute elements and additional speedup due to improvement in the clock frequency (up to 30%). The clock period reduction is made possible because computation and accesses are now localized, i.e. the compute elements interact only with memories which are close by.

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Compiling SA-C Programs to FPGAs: Performance Results

Cited by 15 publications

References 2 publications

Portable, Flexible, and Scalable Soft Vector Processors

Portable, Flexible, and Scalable Soft Vector Processors

A stochastic bitwidth estimation technique for compact and low-power custom processors

A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures

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